cy29949中文资料
7页1、2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer CY29949 Cypress Semiconductor Corporation3901 North First StreetSan Jose,CA 95134408-943-2600 Document #: 38-07289 Rev. *D Revised November 6, 2003 Features 2.5V or 3.3V operation 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS-/LVTTL-compatible outputs 15 clock outputs: drive up to 30 clock lines 1X and 1/2X configurable outputs Output three-state control 350 ps max. output-to-output skew Pin compatible with MPC949, MPC9449 Ava
2、ilable in Commercial and Industrial temp. range 52-pin TQFP package Description The CY29949 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or LVTTL compatible and can drive 50 series or parallel termi- nated transmissio
3、n lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:30. The CY29949 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs. The CY29949 outputs can also be three-stated via the MR/OE# input. When MR/OE# is set HIGH, it resets
4、 the internal flip-flops and three-states the outputs. Block Diagram Pin Configuration MR/OE# TCLK_SEL VDD TCLK0 TCLK1 PECL_CLK PECL_CLK# PCLK_SEL DSELA DSELB DSELC DSELD VSS NC VDDC QD4 VSS QD3 VDDC QD2 VSS QD1 VDDC QD0 VSS NC NC VDDC QB2 VSS QB1 VDDC QB0 VSS VSS QA1 VDDC QA0 VSS NC VSS QC0 VDDC QC1 VSS QC2 VDDC QC3 VSS VSS QD5 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 CY29949 0 1 1 2 0 1
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