CMOS模拟集成电路设计教学课件(英文版)共33章04.pdf

Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-1 CMOS Analog Circuit Design P.E.Allen-2016 LECTURE 04-ULTRA-DEEP SUBMICRON AND BiCMOS TECHNOLOGIES LECTURE ORGANIZATION Outline Ultra-deep submicron CMOS technology -Features -Advantages -Problems BiCMOS technology process flow -CMOS is typical submicron(0.5 m)Summary CMOS Analog Circuit Design,3rd Edition Reference New material Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-2 CMOS Analog Circuit Design P.E.Allen-2016 ULTRA-DEEP SUBMICRON(UDSM)CMOS TECHNOLOGY USDM Technology Lmin 0.1 microns Minimum feature size less than 100 nanometers Todays state of the art:-22 nm drawn length -5 nm lateral diffusion(12 nm gate length)-1 nm transistor gate oxide -8 layers of copper interconnect Specialized processing is used to increase drive capability and maintain low off currents Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-3 CMOS Analog Circuit Design P.E.Allen-2016 65 Nanometer CMOS Technology TEM cross-section of a 35 nm NMOS and PMOS transistors.NMOS:PMOS:These transistors utilize enhanced channel strains to increase drive capability and to reduce off currents.P.Bai,et.Al.,“A 65nm Lobic Technology Featuring 35nm Gate Lengths,Enhanced Channel Strain,8 Cu Interconnect Layers,Low-k ILD and 0.57 m2 SRAM Cell,IEEE Inter.Electron Device Meeting,Dec.12-15,2005.220 nm pitch NMOS Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-4 CMOS Analog Circuit Design P.E.Allen-2016 UDSM Metal and Interconnects Physical aspects:Layer Pitch(nm)Thickness(nm)Aspect Ratio Isolation 220 230-Polysilicon 220 90-Contacted Gate Pitch 220-Metal 1 210 170 1.6 Metal 2 210 190 1.8 Metal 3 220 200 1.8 Metal 4 280 250 1.8 Metal 5 330 300 1.8 Metal 6 480 430 1.8 Metal 7 720 650 1.8 Metal 8 1080 975 1.8 Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-5 CMOS Analog Circuit Design P.E.Allen-2016 What are the Advantages of UDSM CMOS Technology?Digital Viewpoint:Improved Ion/Ioff 70 Mbit SRAM chip:Reduced gate capacitance Higher drive current capability Reduced interconnect density Reduction of active power Analog Viewpoint:More levels of metal Higher fT Higher capacitance density Reduced junction capacitance per gm More speed Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-6 CMOS Analog Circuit Design P.E.Allen-2016 What are the Disadvantages of UDSM CMOS Technology(for Analog)?Reduction in power supply resulting in reduced headroom Gate leakage currents Reduced small-signal intrinsic gains Increased nonlinearity(IIP3)Increased noise and poorer matching(smaller area)Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:Anne-Johan Annema,et.Al.,“Analog Circuits in Ultra-Deep-Submicron CMOS,”IEEE J.of Solid-State Circuits,Vol.40,No.1,Jan.2005,pp.132-143.Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-7 CMOS Analog Circuit Design P.E.Allen-2016 What is the Gate Leakage Problem?Gate current occurs in thin oxide devices due to direct tunneling through the thin oxide.Gate current depends on:1.)The gate-source voltage(and the drain-gate voltage)iGS=K1vGS exp(K2vGS)and iGD=K3vGD exp(K4vGD)2.)Gate area NMOS leakage 6nA/m2 and PMOS leakage 3nA/m2 Unfortunately,the gate leakage current is nonlinear with respect to the gate-source and gate-drain voltages.A possible model is:Base current cancellation schemes used for BJTs are difficult to apply to the MOSFET.051205-03f(vGS)f(vGD)+-vGD+-vGSf(vDG)f(vSG)+-vSG+-vDGNMOSPMOSLarge Signal ModelsggdggsNMOSgsggdgPMOSSmall Signal ModelsLecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-8 CMOS Analog Circuit Design P.E.Allen-2016 UDSM CMOS Technology Summary Increased transconductance and frequency capability Low power supply voltages Reduced parasitics Gate leakage causes challenges for analog applications of UDSM technology -Can no longer use the MOSFET for capacitance -Conflict between matching and gate leakage Other issues -Noise -Zero temperature coefficient behavior -Etc.Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-9 CMOS Analog Circuit Design P.E.Allen-2016 BiCMOS TECHNOLOGY Typical 0.5m BiCMOS Technology Masking Sequence:1.Buried n+layer 9.Base oxide/implant 17.Contacts 2.Buried p+layer 10.Emitter implant 18.Metal 1 3.Collector tub 11.Poly 1 19.Via 1 4.Active area 12.NMOS lightly doped drain 20.Metal 2 5.Collector sinker 13.PMOS lightly doped drain 21.Via 2 6.n-well 14.n+source/drain 22.Metal 3 7.p-well 15.p+source/drain 23.Nitride passivation 8.Emitter window 16.Silicide protection Notation used in the following slides:BSPG=Boron and Phosphorus doped Silicate Glass(oxide)Kooi Nitride=A thin layer of silicon nitride on the silicon surface as a result of the reaction of silicon with the HN3 generated,during the field oxidation.TEOS=Tetro-Ethyl-Ortho-Silicate.A chemical compound used to deposit conformal oxide films.Lecture 04 UDSM and BiCMOS Technologies(3/10/14)Page 04-10 CMOS Analog Circuit Design P.E.Allen-2016 n+and p+Buried Layers Starting Substrate:n+and p+Buried Layers:。