第六章电路参数及其提取资料教程.ppt

1 1Department of Microelectronics, PKU，Xiaoyan Liu第六章电路参数及其提取第一节 信号传输延迟第二节 功 耗2 2Department of Microelectronics, PKU，Xiaoyan Liu第一节 信号传输延迟数字电路的延迟由四部分组成：v 门延迟v 连线延迟v 扇出延迟v 大电容延迟3 3Department of Microelectronics, PKU，Xiaoyan Liu由与输出节点相关的微分方程描述近似处理简化的RC充放电近似tp = 0.69 CL (Reqn+Reqp)/2ln(2)一、CMOS门延迟4 4Department of Microelectronics, PKU，Xiaoyan Liu5 5Department of Microelectronics, PKU，Xiaoyan Liu二、连线延迟interwirefringepp6 6Department of Microelectronics, PKU，Xiaoyan Liu描述引线RC延迟的模型可以分为集总模型（lumped model）和分布模型（distributed model） 集总模型RC延迟cwireDrivercapacitance per unit lengthVoutClumpedRDriverVout简单适于短引线(r,c,L)VNVinrLVinVNrLrLrLrLcLcLcLcLcLr,c单位长度的引线电阻、电容7 7Department of Microelectronics, PKU，Xiaoyan Liu分布模型（distributed model）RC延迟节点i的电压所满足的方程网络节点分得很密延迟时间与连线的长度的平方成正比！长连线加驱动器缓冲器buffer反相器链8 8Department of Microelectronics, PKU，Xiaoyan Liu门延迟和引线延迟一起考虑RDriverVinVoutrw,cw,L 门延迟和引线延迟的总延迟时间为t= 0.69RDriverCw + (RwCw)/2 = RDriverCw + 0.5rwcwL2 Rw = rwL , Cw = cwL长连线加驱动器缓冲器buffer反相器链9 9Department of Microelectronics, PKU，Xiaoyan LiuCLKPAD1500Cu500Cu1200Cu750CuCubuffer0buffer1buffer2buffer3buffer4CLK1CLK2CLK3CLK4三、电路扇出延迟 逻辑门的输出端所接的输入门的个数称为电路的扇出：Fout。

对于电路扇出参数的主要限制是：1111Department of Microelectronics, PKU，Xiaoyan Liu 扇出端的负载等于每个输入端的栅电容之和： 在电路设计中， 如果一个反相器的扇出为N，即Fout=N其驱动能力应提高N倍，才能获得与其驱动一级门相同的延迟时间否则它的上升及下降时间都会下降N倍1212Department of Microelectronics, PKU，Xiaoyan Liu 采用加入缓冲器使大扇入和大扇出相隔离CLCL四、大电容负载驱动电路 问题：一个门驱动非常大的负载时，会引起延迟的增大由于外部电容比芯片内部标准门栅电容可能要大几个数量级要想在允许的门延迟时间内驱动大电容负载，只有提高 即增大W，将使栅面积LW增大，管子的输入电容（即栅电容）Cg也随之增大，它相对于前一级又是一个大电容负载问题并没有解决？ Mead和Conway论证了用逐级放大反相器构成的驱动电路可有效地解决驱动大电容负载问题1414Department of Microelectronics, PKU，Xiaoyan Liu设计关键：驱动负载CL需要多少级才能使延迟最小？每级反相器的尺寸如何确定？M1515Department of Microelectronics, PKU，Xiaoyan Liu驱动负载时反相器的延迟Delay=Delay(本征） Delay(负载）设Wp2Wn2W时上拉和下拉的电流相同，即有相同的上升和延迟时间等价于RC网络对于反相器链有：Cgin，j未知若反相器间保持固定的比例则设每级间的尺寸比为f，即每级有相同的延迟对于给定的负载CL和输入电容Cin，可以确定其比例F，从而得到延迟最小条件下的优化尺寸忽略了反相器自身的负载，本征负载Cint1818Department of Microelectronics, PKU，Xiaoyan Liu1919Department of Microelectronics, PKU，Xiaoyan Liu反相器链举例2020Department of Microelectronics, PKU，Xiaoyan LiuLogical Effort 延迟模型一般分析逻辑门的延迟是基于负载的，若要准确计算需要精确的寄生参数和版图信息。

但在逻辑设计和电路设计阶段，无法得到这些信息，因此需要新的模型对延迟进行预算，而不必基于准确的寄生参数Logical Effort，LE通过比较不同逻辑结构的延迟，评估CMOS电路的延迟2121Department of Microelectronics, PKU，Xiaoyan Liu门延迟: gate delayd = h + peffort delayintrinsic delayEffort delay:h = g flogical efforteffective fanout = Cout/CinLogical effort 与电路拓扑结构相关，与器件的尺寸无关Effective fanout (electrical effort) 是负载和器件尺寸的函数逻辑门中的延迟门延迟的仔细区分依赖于负载和逻辑特性依赖寄生特性2222Department of Microelectronics, PKU，Xiaoyan LiuLogical Effort 反相器的logical effort 和 intrinsic delay 是所有静态CMOS 门中最小的，取为1 Logical effort 是该逻辑门和反相器在流过相同电流的条件下逻辑门的输入电容与反相器的输入电容的比值，它独立于MOSFET的尺寸 逻辑门越复杂，Logical effort 越大Logical effort 是该逻辑门和反相器在流过相同电流的条件下逻辑门的输入电容与反相器的输入电容的比值g = 1g = 4/3g = 5/3A + BABABABA BABAAA21Cunit = 32222Cunit = 44411Cunit = 52424Department of Microelectronics, PKU，Xiaoyan Liu各输入端的LE可能不一样ABC2525Department of Microelectronics, PKU，Xiaoyan LiuLogical Effort2626Department of Microelectronics, PKU，Xiaoyan Liu对于非标准逻辑门和非标准但K相同的反相器比等效反相器为2727Department of Microelectronics, PKU，Xiaoyan LiuLogical Effort of GatesFan-out (h) Normalized delay (d)t1 23 4 5 6 7 pINVtpNANDF(Fan-in)g = 1p = 1d = h+1g = 4/3p = 2d = (4/3)h+22828Department of Microelectronics, PKU，Xiaoyan Liud = h + pg fp对于扇出为4的标准反相器g=1, f=4 若g0，p0, d=gf+p=4若g 1，p1, d=gf+p=5对于N级标准反相器构成的环振g=1, f=1若g 0，p0, d1=gf+p=1DNd1N， freq1/2*N若g 1，p1, d1=gf+p=2DNd12*N， freq1/4*N2929Department of Microelectronics, PKU，Xiaoyan LiuStage effort: hi = gifiPath electrical effort: F = Cout/CinPath logical effort: G = g1g2gNBranching effort: B = b1b2bNPath effort: H = GFBPath delay D = Sdi = Spi + ShiN级逻辑门相连3030Department of Microelectronics, PKU，Xiaoyan LiuBranching effort: 有分支的情况3131Department of Microelectronics, PKU，Xiaoyan Liu优化设计当每一级具有相同effort delay时，为最优设计:N级的最小延迟为每一级的等效扇出为:即 Stage efforts: g1f1 = g2f2 = = gNfN3232Department of Microelectronics, PKU，Xiaoyan Liu对于给定的负载CL和给定的第一级的输入电容Cin, 可以证明最优的级数N和级间比例为：称为 best stage effort3333Department of Microelectronics, PKU，Xiaoyan Liu 计算出总的: F = GBH 估算出总级数 计算 stage effort f = F1/N 按所需的级数实现逻辑功能 逐级确定尺寸: Cin = Cout*g/fReference: Sutherland, Sproull, Harris, “Logical Effort”, Morgan-Kaufmann 1999.优化设计方法3434Department of Microelectronics, PKU，Xiaoyan Liu例：确定下列电路的尺寸，使延迟最小g = 1f = ag = 5/3f = b/ag = 5/3f = c/bg = 1f = 5/cEffective fanout, F = 5G = 25/9H = FBG=125/9 = 13.9h = 1.93H1/4a = 1.93b = ha/g2 = 2.23c = hb/g3 = 5g4/f = 2.59hgf1abcCL53535Department of Microelectronics, PKU，Xiaoyan Liu3636Department of Microelectronics, PKU，Xiaoyan Liu 第二节 功 耗 在功耗设计中主要考虑三个因素：一 导体的电迁移现象；二 散热问题；三 供电问题。

3737Department of Microelectronics, PKU，Xiaoyan LiuP6Pentium 486386286808680858080800840040.1110100197119741978198519922000YearPower (Watts)微处理器的功耗不断增加功耗及其散热将成为限制集成电路缩小的主要因素为什么需要考虑功耗? 芯片的功率密度40048008808080858086286386486PentiumP611010010001000019701980199020002010YearPower Density (W/cm2)Hot PlateNuclearReactorRocketNozzleSunsSurfacechips might become hot为什么需要考虑功耗? 电池的体积/重量Expected battery lifet。