21ic下载_CYCLONE的EP1C6Q240C8开发板原理图 (1)

1、5 5 4 4 3 3 2 2 1 1 DD CC BB AA P14 HCSn P13 MCU_RESET HR/Wn HCNTL1 HCNTL0 HBIL DSP_RESET RXD_MCU P12 TXD_MCU MCU_TDI MCU_TDO MCU_TCK WRn HPIINT RDn MCU_RESET P14 P13 P12 SDAT SCLK SCS HPID0 HPID1 HBIL MCU_TEST HPID2 HCNTL0 HPID3 HCNTL1 HPID4 HR/Wn HPID5 ALE HPID6 HCSn MCU_TEST HPID7 INT0 INT1 INT3 EMU0 TMS TCK TDI EMU1 DSP_RESET SW0 HPIENA SW2 SW3 TDO TRSTn EMU1 NMI HCNTL0 RDn PSn HBIL HR/Wn HPIINT HCSn HPIENA D0:15A0:22 ISn CLK_MD3 D0 D1 D2 D3 D4 D5 D6 D7 CLK_MD1 D8 D9 D10 CLK_MD2 D11 D12 D13

2、D14 D15 CLK_MD2 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 CLK_MD1 A1 A2 A3 A4 A5 A6 A0 CLK_MD3 IOSTRBn MSTRBn DSP_RESET DSP_RW TCK TDI TDO TMS TRSTn EMU0 HPID0 EMU1 HPID1 HPID2 NMI HPID3 INT0 HPID4 INT1 HPID5 ALE HPID6 INT3 HPIINT HPID7 HCNTL1 WRn DSn READY A20 A0:20 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DSP_RESET FLASH_CEn FLASH_OEn FLASH_WEn D0:15 A19 A18 A17 A16 A15 B_IN GCLK HS R_IN VS G_IN B_IN GBE0 GBE1 GB

3、E2 GBE3 GBE4 GBE5 GBE6 GBE7 GGE0 GGE1 GGE2 GGE3 GGE4 GGE5 GGE6 GGE7 GRE0 GRE1 GRE2 GRE3 GRE4 GRE5 GRE6 GRE7 GBE07 GGE07 GRE07 GHS GVS SDAT SCLK VS_IN G_IN HS_IN VS_IN R_IN HS_IN DA_B DA_G DA_R DHS DRER9 DRER6 DRER8 DRER7 DRER5 DPEN DCLK DRER3 DRER4 DRER2 DGER9 DGER7 DGER8 DGER6 DGER5 DGER4 DBER4 DBER6 DBER3 DBER9 DBER8 DBER7 DBER5 DBE1 DBE0 DRE1 DGER3 DGE1 DGE0 DGER2 DBER2 DVS DRE0 MCU_TCK MCU_RESET MCU_TDI MCU_TDO SDRAM_A6 SDRAM_A5 SDRAM_A4 SDRAM_A3 SDRAM_A2 SDRAM_A1 SDRAM_A0 SDRAM_A11 SDRAM_A1

4、0 SDRAM_A9 SDRAM_A8 SDRAM_A7 DQM WE SDRAM_CLK CAS RAS SDRAM_D0 SDRAM_D1 SDRAM_D2 SDRAM_D3 SDRAM_D4 SDRAM_D5 SDRAM_D6 SDRAM_D7 SDRAM_D8 SDRAM_D9 SDRAM_D10 SDRAM_D11 SDRAM_D12 SDRAM_D13 BANK0 BANK1 SDRAM_A11:0 SDRAM_D15:0 SDRAM_D14 SDRAM_D15 TXD RXD GND_1C12_0 VCCINT_1C12_0 VCCINT_1C12_1 GND_1C12_1 VCCINT_1C12_2 GND_1C12_2 VCCINT_1C12_3 GND_1C12_3 VCCINT_1C12_4 GND_1C12_4 VCCINT_1C12_5 GND_1C12_5 VCCINT_1C12_0 VCCINT_1C12_1 VCCINT_1C12_2 VCCINT_1C12_3 VCCINT_1C12_4 VCCINT_1C12_5 GND_1C12_2 GND_1C1

5、2_3 GND_1C12_4 GND_1C12_5 GND_1C12_0 GND_1C12_1 COSC0 MSTRBn DSP_RW ISn FLASH_WEn PSn READY A15 DSn A13 A12 A11 A14 A5 A8 A7 A6 A2 A1 A0 A4 A3 D11 D10 D13 D12 D5 D9 D6 D7 D8 D3 D4 LED0 RXD_MCU FLASH_OEn INT0 SW2 TXD_MCU LED1 A10 SDAT TXD RXD GVS KEY0 SCLK GHS GRE5 GRE6 GRE4 GRE1 GRE2 GRE3 GRE0 GGE6 GGE7 GGE2 GBE7 GGE0 GGE1 GBE6 GBE4 GBE5 GBE3 VD7 GBE1 GBE2 KEY1 GCLK COSC0 VD2 VD3 VD5 VD6 VD1 VD0 DRE5 DRE8 DRE6 DRE7 DRE9 DGE3 DGE2 DGE4 DBE3 DBE2 DPEN DVS D0 DBE6 DBE8 DBE5 DGE5 DGE6 DBE9 DBE7 D1 D

6、2 DBE4 BANK0 BANK1 SDRAM_A10 SDRAM_A0 RAS CAS WE DQM SDRAM_D7 SDRAM_D5 SDRAM_D4 DRE4 DRE3 SDRAM_A2 SW3 DRE2 DHS D14 GGE4 GGE5 VE5 VE6 VE7 DRER9 DRER6 DRER5 DRER8 DRER7 VE3 VE4 VE1 VE2 DRER3 DRER2 VE0 DRER4 SVIDEO_OUTY SVIDEO_OUTC DCLK DHS DVS DPEN SDAT SCLK VE_RESETn VE_RESETn SVIDEO_OUTC SVIDEO_OUTY SVIDEO_OUTY SVIDEO_OUTC SDRAM_A1 SDRAM_D6 GBE0 VE0 DGE7 FLASH_CEn VD4 GGE3 GRE7 D15 A9 IOSTRBn DGE8 DGE9 LED0 LED1 KEY1 KEY0 IR PPI_CLK IR SW0 SW0 SCLk SDAT DRE2 DRE3 DRE4 DRE5 DRE8 DRE9 DRE6 DRE7 D

7、GE4 DGE5 DGE8 DGE9 DGE6 DGE7 DGE2 DGE3 DBE4 DBE5 DBE8 DBE9 DBE6 DBE7 DBE2 DBE3 DRER4 DRER5 DRER8 DRER9 DRER6 DRER7 DRER2 DRER3 DGER4 DGER5 DGER8 DGER9 DGER6 DGER7 DGER2 DGER3 DBER4 DBER5 DBER8 DBER9 DBER6 DBER7 DBER2 DBER3 DCLK XTAL XTAL1 SCLK SDAT VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 PPI_CLK AI12 VHS FIELD VVS AI12 SDRAM_D15 VHS VVS FIELD SDRAM_D14 SDRAM_D13 SDRAM_D12 SDRAM_D11 SDRAM_D10 SDRAM_D9 SDRAM_D8 SDRAM_D0 SDRAM_D1 SDRAM_D2 SDRAM_D3 VE2 VE7 VE5 VE4 VE3 VE6 VE1 SDRAM_CLK SDRAM_A9 SDRAM_A11 SD

8、RAM_A3 SDRAM_A8 SDRAM_A4 SDRAM_A5 SDRAM_A7 SDRAM_A6 5V 5V 5V 5V 5V 5V VCC 3V3 3V3 VCC 1V8 VCC 3V3 1V8 3V3 VCC 3V3 3V3 3V3 3V3 3V3 3V3 3V3_AD 3V3_AD 3V3_AD 3V3_AD 3V3_AD 5V_DA GND GND GND GND GND GND GND GND 3V3 3V3 3V3 3V3RAMVDD RAMVDD RAMVDD 3V3_9883 5V 5V GND GND GND GND 1V53V31V5 1V5 1V53V3 3V3 5V5V_VE 5V_VE 5V_VE 5V_VE 5V_VE 5V_VE 5V_VE 3V3 5V_VE 9V 3V3 GND 9V VCC GND GND GND VCC 9V 1V8 9V 5V 9V 1V5 9V 3V3_9883 GND GND 3V3 3V3 VCC 3V3 3V3_7113 3V3_7113 ADC_VD1A 3V3_7113 3V3_7113 9V3V3 Title

9、SizeDocument NumberRev Date:Sheetof 1.2 DSP + FPGA Video Board E 11Monday, February 23, 2009 Title SizeDocument NumberRev Date:Sheetof 1.2 DSP + FPGA Video Board E 11Monday, February 23, 2009 Title SizeDocument NumberRev Date:Sheetof 1.2 DSP + FPGA Video Board E 11Monday, February 23, 2009 MCU CONTROL DSP RESET DSP JTAG MAIN Video DAC PIN JUMPER FOR EP1C12 DEVICE Optional Oscillator For 100MHz CLOCK VIDEO ENCODER POWER INPUT 7.5V-12V POWER Analog and digital power dissipation =0.4W 3.3V Digital supply current max=35mA Analog supply current max=90mA C48 0.1U C48 0.1U C21 0.1U C21 0.1U D5 LED D5 LED C6 100NF C6 100NF RM17 75F RM17 75F L480BEADL480BEAD RM40 56 RM40 56 R21 10K R21 10K CM30 0.1U CM30 0.1U C12 0.1U C12 0.1U RPM5 22*4 RPM5 22*4 1 3 5 78 6 4 2 J7 VD_PDJUMP J7 VD_PDJUMP 1 2 10k RP2 10k RP2 78 56 34 12 10k RP1 10k RP1 78 56 34 12 C24 22U/16V C24 22U/16V J9 SPI CON J9 SPI CON 1 2 3 4 5 6 7 8 9 10 11 12 13 14 U4 SP232 U4 SP232 C1+ 1 V+ 2 C1- 3 C2- 5 V- 6 C2+ 4

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