fm24c64b 铁电存储器.pdf

Preliminary This is a product that has fixed target specifications but are subject Ramtron International Corporation to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 Rev. 1.3 Feb. 2011 Page 1 of 12 FM24C64B 64Kb Serial 5V F-RAM Memory Features 64K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High Endurance 1 Trillion (1012) Read/Writes • 38 Year Data Retention • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface • Up to 1 MHz maximum bus frequency • Direct hardware replacement for EEPROM • Supports legacy timing for 100 kHz & 400 kHz Low Power Operation • 5V operation • 100 µA Active Current (100 kHz) • 4 µA (typ.) Standby Current Industry Standard Configuration • Industrial Temperature -40° C to +85° C • 8-pin “Green”/RoHS SOIC (-G) Description The FM24C64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM24C64B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM24C64B is capable of supporting 1012 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM24C64B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writes with less overhead for the system. The FM24C64B provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24C64B is available in an industry standard 8-pin SOIC package and uses a familiar two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration A0 A1 A2 VSS VDD WP SCL SDA 1 2 3 4 8 7 6 5 Pin Names Function A0-A2 Device Select Address SDA Serial Data/address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage Ordering Information FM24C64B-G “Green”/RoHS 8-pin SOIC FM24C64B-GTR “Green”/RoHS 8-pin SOIC, Tape & Reel FM24C64B Rev. 1.3 Feb. 2011 2 of 12 Address Latch 1,024 x 64 FRAM Array 8 SDA Counter Serial to Parallel Converter Control Logic SCL WP A0-A2 Data Latch Figure 1. FM24C64B Block Diagram Pin Description Pin Name I/O Pin Description A0-A2 Input Address 2-0: These pins are used to select one of up to 8 devices of the same type on the same two-wire bus. To select the device, the address value on the three pins must match the corresponding bits contained in the device address. The address pins are pulled down internally. SDA I/O Serial Data Address: This is a bi-directional pin used to shift serial data and addresses for the two-wire interface. It employs an open-drain output and is intended to be wire- OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. A pull-up resistor is required. SCL Input Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL input also incorporates a Schmitt trigger input for improved noise immunity. WP Input Write Protect: When WP is high, addresses in the upper quadrant of the logical memory map will be write-protected. Write access is permitted to the lower three- quarters of the address space. When WP is low, all addresses may be written. This pin is pulled down internally. VDD Supply Supply Voltage: 5V VSS Supply Ground FM24C64B Rev. 1.3 Feb. 2011 3 of 12 Overview The FM24C64B is a serial FRAM memory. The memory array is logically organized as a 8,192 x 8 bit memory array and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM24C64B and a serial EEPROM with the same pinout relates to its superior write performance. Memory Architecture When accessing the FM24C64B, the user addresses 8,192 locations each with 8 data bits. These data bits are shifted serially. The 8,192 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish from other non-memory devices), and an extended 16-bit address. Only the lower 13 bits are used by the decoder for accessing the me。