计算机组成与设计第四章答案（第三版第四版通用）

1、 4 Solutions Solution 4.1 4.1.1 The values of the signals are as follows: RegWriteMemReadALUMuxMemWriteALUOpRegMuxBranch a.100 (Reg)0Add1 (ALU)0 b.111 (Imm)0Add1 (Mem)0 ALUMux is the control signal that controls the Mux at the ALU input, 0 (Reg) selects the output of the register fi le and 1 (Imm) selects the immediate from the instruction word as the second input to the ALU. RegMux is the control signal that controls the Mux at the Data input to the regis- ter fi le, 0 (ALU) selects the output

2、of the ALU and 1 (Mem) selects the output of memory. A value of X is a “dont care” (does not matter if signal is 0 or 1) 4.1.2 Resources performing a useful function for this instruction are: a.All except Data Memory and branch Add unit b.All except branch Add unit and second read port of the Registers 4.1.3 Outputs that are not usedNo outputs a. Branch AddData Memory b. Branch Add, second read port of RegistersNone (all units produce outputs) 4.1.4 One long path for and instruction is to read t

3、he instruction, read the reg- isters, go through the ALUMux, perform the ALU operation, and go through the Mux that controls the write data for Registers (I-Mem, Regs, Mux, ALU, and Mux). The other long path is similar, but goes through Control while registers are read (I- Mem, Control, Mux, ALU, Mux). There are other paths but they are shorter, such as the PC increment path (only Add and then Mux), the path to prevent branching (I-Mem, Control, Mux uses Branch signal to select the PC + 4 input

4、as the new value for PC), the path that prevents a memory write (only I-Mem and then Control, etc). S110 Chapter 4 Solutions a.Control is faster than registers, so the critical path is I-Mem, Regs, Mux, ALU, Mux. b.Control is faster than registers, so the critical path is I-Mem, Regs, Mux, ALU, Mux. 4.1.5 One long path is to read instruction, read registers, use the Mux to select the immediate as the second ALU input, use ALU (compute address), access D-Mem, and use the Mux to select that as reg

5、ister data input, so we have I-Mem, Regs, Mux, ALU, D-Mem, Mux. The other long path is similar, but goes through Control instead of Regs (to generate the control signal for the ALU MUX). Other paths are shorter, and are similar to shorter paths described for 4.1.4. a.Control is faster than registers, so the critical path is I-Mem, Regs, Mux, ALU, D-Mem, Mux. b.Control is faster than registers, so the critical path is I-Mem, Regs, Mux, ALU, Mux. 4.1.6 This instruction has two kinds of long paths,

6、 those that determine the branch condition and those that compute the new PC. To determine the branch condition, we read the instruction, read registers or use the Control unit, then use the ALU Mux and then the ALU to compare the two values, then use the Zero out- put of the ALU to control the Mux that selects the new PC. As in 4.1.4 and 4.1.5: a. The fi rst path (through Regs) is longer. b. The fi rst path (through Regs) is longer. To compute the PC, one path is to increment it by 4 (Add), add

7、 the offset (Add), and select that value as the new PC (Mux). The other path for computing the PC is to Read the instruction (to get the offset), use the branch Add unit and Mux. Both of the compute-PC paths are shorter than the critical path that determines the branch condition, because I-Mem is slower than the PC + 4 Add unit, and because ALU is slower than the branch Add. Solution 4.2 4.2.1 Existing blocks that can be used for this instruction are: a.This instruction uses instruction memory,

8、both existing read ports of Registers, the ALU, and the write port of Registers. b.This instruction uses the instruction memory, one of the existing register read ports, the path that passed the immediate to the ALU, and the register write port. 4.2.2 New functional blocks needed for this instruction are: a.Another read port in Registers (to read Rx) and either a second ALU (to add Rx to Rs + Rt) or a third input to the existing ALU. b.We need to extend the existing ALU to also do shifts (adds a

9、 SLL ALU operation). Chapter 4 Solutions S111 4.2.3 The new control signals are: a.We need a control signal that tells the new ALU what to do, or if we extended the existing ALU we need to add a new ADD3 operation. b.We need to change the ALU Operation control signals to support the added SLL operation in the ALU. 4.2.4 Clock cycle time is determined by the critical path, which for the given latencies happens to be to get the data value for the load instruction: I-Mem (read instruction), Regs (takes longer than Control), Mux (select ALU input), ALU, Data Memory, and Mux (select value from memory to be written into Registers). The latency of this path is 400ps + 200ps + 30ps + 120ps + 350ps + 30ps = 1130ps. New clock cycle time a. 1130ps (No change, Add units are not on the critical path). b. 1230 (1130ps + 100ps, Regs are on the critical path) 4.2.5 The speed-up comes from changes in clock cycle time and changes to the number of clock cycles we need for the program: Benefi t a. Speed-

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