DRAM内存颗粒测试简介PPT课件(PPT 37页).ppt

Introduction to DRAM Testing--- DRAM inside team--- 2015.May第1页，共37页AgendanBasis of TestingnTypical DRAM Testing FlownBurn-innDC Test (Open/Short, Leakage, IDD)nFunctional Test & Test PatternnSpeed Test第2页，共37页DRAM ManufactureWaferAssemblyFinal TestingFinal Product第3页，共37页Why Testing?¨To screen out defect•Wafer defect•Assembly defect¨Make sure product meet spec of customer•Voltage guard band•Temperature guard band•Timing guard band•Complex test pattern¨Collect data for design & process improvement•Quality•Reliability•Cost•Efficiency第4页，共37页。

IC Test MethodologyIC TesterPPSDriverComparatorDUT** DUT = Device Under TestPower SupplyOutputInputTesting of a DUT: 1. To connect PPS, Driver, Comparator & GND. 2. To apply power to DUT. 3. To input data to DUT (Address, Control Command, Data) 4. To compare output with “expect value” and judge PASS/FAIL第5页，共37页Basic Test Signal¨Digital Waveform Elements•Logic•Voltage•Timing第6页，共37页Typical DRAM Final Test FlowBurn-in•MBT (Monitor Burn in Test): Stress to screen out Early Failures•TBT (Test Burn in Test): Long time pattern test•Very Low Speed(5-20MHz), High Parallel Test (10-20Kpcs/oven), Low CostCore Test•DC Test•Functional Test•Low Speed (DDR3 @667MHz), Typical tester Advantest T5588 + 512DUT HiFixSpeed Test•Speed & AC Timing Test•Full Speed (DDR3 @1600MHz and above), Advantest T5503 + 256DUT HiFixBackend•Marking  Ball Scan  Visual Inspection  Baking  Vacuum Pack 第7页，共37页。

DRAM Burn-in (MBT)MBT is to stress IC and screen out early failures¨High Temperature Stress (125degC)¨High Voltage Stress¨Stressful Pattern BIOperation TimeFailure RateInfant MortalityNormal LifeWorn outNew productMature productBath Curve第8页，共37页DRAM Burn-in (TBT)TBT is for long time test patterns¨Multiple temperature tested (e.g. 88’C, 25’C, -10’C)¨Long test time at low speed¨Patterns cover all cell arrays¨No Stressful condition¨High parallel test count, low cost¨Both MBT and TBT does NOT test DC (Ando Oven)第9页，共37页。

DRAM Advantest Test1.1.DC Test¨Open/Short test¨Leakage test¨IDD test2.2.Functional Test (Core Test)¨Different parameter & Pattern for each function¨To check DRAM can operate functionally3.3.Speed Test¨Timing test @ different speed grade第10页，共37页DC Test DC Test Method:DC Test Method:a)a)ISVMISVM: :I SI SourceourceV MV Measureeasureb)b)VSIMVSIMV SV SourceourceI MI MeasureeasureVCCVCC第11页，共37页DC Test – Open ShortPurpose: • Check connection between pins and test fixture• Check if pin to pin is short in IC package• Check if pin to wafer pad has open in IC package• Check if protection diodes work on die• It is a quick electrical check to determine if it is safe to apply power• Also called Continuity Test第12页，共37页。

DC Test – Open ShortFailure Mode:a) Wafer ProblemDefect of diodeb) Assembly ProblemWire bondingSolder ballc) Contact ProblemSocket issueCore CircuitDefective diodeSocket Pogo Pin defectWire touched第13页，共37页DC Test – Open ShortO/S Test Condition:Procedure•Ground all pins ( including VDD)•Using PMU force 100 uA, one pin at a time•Measure voltage•Fail open test if the voltage is greater than 1.5 V•Fail short test if the voltage is less than 0.2 V100uA0.65 VPMUforcesenseforceMeasureVss=0Vdd=0100uAFail OpenPassFail Short> 1.5V< 0.2VISVMOther=0Typical 0.65V第14页，共37页。

DC Test – Open ShortO/S Test Condition:Procedure•Ground all pins ( including VDD)•Using PMU force –100 uA, one pin at a time•Measure voltage•Fail open test if the voltage is less than –1.5 V•Fail short test if the voltage is greater than –0.2 VFail ShortPassFail Open> –0.2 V<–1.5 V-100uA-0.65 VPMUforcesenseforceMeasureVss=0Vdd=0-100uAISVMOther=0Typical -0.65V第15页，共37页DC Test – LeakagePurpose: • Verify resistance of pin to VDD/VSS is high enough• Verify resistance of pin to pins is high enough• Identify process problem in CMOS device 第16页，共37页。

DC Test – LeakageILIH/ILIL: Input Leakage High/Low• To verify input buffers offer a high resistance • No preconditioning pattern appliedILOH/ILOL: Output Leakage High/Low• To verify tri-state output buffers offer a high resistance in off state• Test requires preconditioning pattern• Performed only on three-state outputs and bi-directional pins第17页，共37页DC Test – LeakageFailure Mode:a) Wafer problemb) Assembly problemc) Socket Contact problem (short)Die crackBall touch (Short)第18页，共37页DC Test – Input Leakage LowTest Condition:Test Condition:Procedure•Apply VDDmax (2.0V)•Pre-condition all input pins to logic ‘1’ (high voltage)•Using PMU (Parametric Measure Unit) force Ground to tested pin•Wait for 1 to 5 msec•Measure current of tested pin•Fail IIL test if the current is less than –1.5 uAPassFail< –1.5 uA0 V-10nAPMUforceMeasureVss=0VDDmaxILILVLSICore“0”“1” all input pins = 2.3VOFFON第19页，共37页。

DC Test – Input Leakage HighTest Condition:Test Condition:Procedure•Apply VDDmax (2.0V)•Pre-condition all input pins to logic ‘0’ (Low voltage)•Using PMU force VDDMAX to tested pin•Wait for 1 to 5 msec•Measure current of tested pin•Fail IIH test if the current is greater than +1.5 uAPassFail> 1.5 uA2.0 V10nAPMUforceMeasureVss=0VDDmaxILIHVLSICore“1”“0” all input pins = 0VONOFF第20页，共37页DC Test – Output Leakage LowTest Condition:Test Condition:Procedure•Apply VDDmax (2.0V)•Pre-condition the DUT to tristate with specific pattern•Wait a specific time•Using PMU force VDDMAX to tested I/O pin•Measure current•Fail IOH test if the current is greater than +4.5uA or less than -4.5uAPassFailGT 4.5 uA0.0 V-10nAPMUforceMeasureVss=0VDDmaxILOLVLSICoreOFFOFFPre-condition Pattern 1/0FailLT -4.5 uA“0”All input pins = 2.3VAll output pins=0V/2.3V第21页，共37页。

DC Test – Output Leakage HighTest Condition:Test Condition:Procedure•Apply VDDmax (2.0V)•Pre-condition the DUT to tristate with specific pattern•Wait a specific time•Using PMU force VDDMAX to tested I/O pin•Measure current•Fail IOH test if the current is greater than +4.5uA or less than -4.5uAPassFailGT 4.5 uA2.0 V10nAPMUforceMeasureVss=0VDDmaxILOHVLSICoreAll input pins = 2.3VAll output pins=0V/2.3VOFFOFFPre-condition Pattern 1/0FailLT -4.5 uA“1”第22页，共37页DC Test – Test Program Condition第23页，共37页。

DC Test – IDDPurpose:nIDD (or ICC) measures current of Vdd pin in different statesnIt makes sure power consumption not higher than expected.Failure Mode:a)Wafer process issueb)Assembly issuec)Contact issue (VDD, VSS)第24页，共37页DC Test – Static IDDTest Condition:Test Condition:Procedure•Using PMU to apply VDDmax on VDD pin•Execute Pre-condition pattern•Stop the pattern•Wait a specific time •Measure current flowing into VDD pins while device is in idle•Fail IDD test if the current is greater than IDD spec. ( Normal in mA)PassFailGT spec2.0 V10mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition Pattern第25页，共37页。

DC Test – Dynamic IDDTest Condition:Test Condition:Procedure•Using PMU to apply VDDmax on VDD pin•Execute Pre-condition pattern•Wait a specific time •Measure current flowing into VDD pins while device is executing pattern•Fail IDD test if the current is greater than IDD spec. ( Normal in mA)•Stop patternPassFailGT spec2.0 V80mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition PatternPre-condition Pattern第26页，共37页Function TestTo verify DRAM can operate functionally, we need to do Functional test.- Easy Function Test (EFT)It check basic IC functionality by reading “0” (or “1”) from all cell after writing “0” (or “1”) in. Typical Test Pattern: March Pattern (e.g. March C-)March C- Algorithm: ↑(w0);↑(r0,w1);↑(r1,w0);↓(r0,w1);↓(r1,w0); ↓(r0)Operation Count: 10*nScan type: X-Scan (X inc -> Y inc), Y-Scan(Y inc -> X inc)Fault Coverage: Most of Failure Mode第27页，共37页。

DRAM Test – 1HTDefect ModeOPENLEAKIDDEFTTESTER RELATED○○○○○○○○WAFER ISSUE○○○○○○○○DIE CRACK○○○○○○DIE CHIP○○○○○○SURFACE DAMAGE○○○○NG Die○○NON DIE○○○○NON WIRE○○A~E OPEN○○WIRE SHORT WITH WIRE○○WIRE SHORT WITH DIE EDGE○○WIRE SWEEP○○NON BROKEN INNER LEAD○○○○OTHERS○○○○○○○○○: SUSPECTION FOR FAILAbove table comes from our experiences. It is not covered all of failure modes vs phenomena. So, it is only for your reference.32.第32页，共37页DRAM Test – Functional TestOther Functional TestCheck Core Function (80% of total test time)¨Data Retention, ODT, Burst Read/Write, …etc¨Detect Pattern Sensitive Fault (PSF)0 0 00 1 00 0 00 0 00 0 00 0 033.第33页，共37页。

DRAM Test – AC TestAC Parameter TestTo verify IC can work as each timing parameter defined in datasheet¨ Rise and fall time¨ Setup and hold time¨ Delay test¨ Others34.第34页，共37页DRAM Test – Speed TestTest DRAM at different speed: 1. DDR3-1600(11-11-11) Test 2. DDR3-1333(9-9-9) Test 3. DDR3-1066(7-7-7) Test Test for each timing (tRCD, tRRD…) ……DDR3-1600DDR3-1333Speed Fail35.第35页，共37页DRAM Test – Test Plan in ProgramO/SO/SLeakageLeakageIDDIDDEFTEFTFUNC TestFUNC TestSpeedSpeed1333Fail1600186636.第36页，共37页。

DRAM inside37.第37页，共37页。