小数分频VHDL代码.docx

小数分频VHDL代码 本文介绍基于前置N/N+1分频器的小数分频基本原理，以及基于此原理的一位小 数分频器的源代码，受数据位宽的影响，本文给出的代码系数整数部分的范围为 0-15，如需更大数值可自行修改代码一、 原理介绍：假设分频系数为N.X,则N*(10-X)+(N+1)*X=10*N-N*X+N*X+X=10*N+X=N.X*10 由上式可见只要满足输出十个脉冲的时间内输入脉冲为10*N+X就可实现N.X分频.可对输入时钟进行 (10-X)次N分频和X次(N+1)分频实现，由于先进行(10-X)次分频后进行X次(N+1) 分频会造成相位有很大变化，可采用N分频和(N+1)分频交替进行的方法来改善 相伴变化. 实现原理不再过多介绍， 请参看 sel 部分源代码二、 源代码1： NdotXfd，顶层文件 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity NdotXfd is port (clock : in std_logic;n : in std_logic_vector(3 downto 0);x clock_out: in std_logic_vector(3 downto 0);: out std_logicend entity;architecture arch of NdotXfd iscomponent numberport(n : in std_logic_vector(3 downto 0); number0 : out std_logic_vector(3 downto 0); number1 : out std_logic_vector(3 downto 0) );end component;component fdnport(clock_in : in std_logic;enable : in std_logic;n_of_fd : in std_logic_vector(3 downto 0); clock_out : out std_logic);end component;component selport(clock_in : in std_logic;Xnumber : in std_logic_vector(3 downto 0); sel_out : out std_logic);end component;component mux_21 port(a : in std_logic; b : in std_logic; s : in std_logic;y : out std_logic );end component;signal selt : std_logic;signal selt_not : std_logic;signal clock_1 : std_logic;signal clock_2 : std_logic;signal clock_sel: std_logic;signal n_fd : std_logic_vector(3 downto 0); signal n1_fd : std_logic_vector(3 downto 0);begin number0 : number port map (n, n_fd, n1_fd);fdn0 : fdn port map (clock, selt_not, n_fd, clock_1);fdn1 : fdn port map (clock, selt, n1_fd, clock_2);mux_210 : mux_21 port map (clock_2, clock_1, selt, clock_sel); sel0 : sel port map (clock_sel, x, selt);selt_not <= not selt; clock_out <= clock_sel;end arch;2:fdn,任意整数分频器（分步系数2—15,可自行修改代码增加分频系数） library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fdn is port (clock_in : in std_logic; enable : in std_logic;n_of_fd : in std_logic_vector(3 downto 0);clock_out : out std_logic);end entity;architecture bhv of fdn issignal clocksignal q0signal q1 signal number signal counter0 signal counter1std_logic;std_logic;std_logic;std_logic_vector(2 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0);beginfdn: process(enable, clock_in, n_of_fd, clock, q0, q1) beginnumber(2 downto 0) <= n_of_fd(3 downto 1);if q1 = '0' thenclock <= not clock_in; elseclock <= clock_in;end if;if (enable='1') thenif (n_of_fd(0)='0')then counter1 <= (others=>'0'); q1 <= '0';if rising_edge(clock_in) then if (number="001") thenq0 <= not q0;elseif counter0 = number-1 thencounter0 <= (others=>'0'); q0 <= not q0;else counter0 <= counter0 + 1; end if;end if;end if;elsecounter0 <= (others=>'0');q0 <= '0';if rising_edge(clock) thenif counter1 = number thencounter1 <= (others=>'0'); q1 <= not q1;else counter1 <= counter1 + 1;end if;end if;end if;elseq0 <= '0';q1 <= '0';counter0 <= (others=>'0');counter1 <= (others=>'0');end if;end process fdn;output: process (enable, n_of_fd(0), q0, q1) beginif (enable='1') thenif (n_of_fd(0)='0')thenclock_out <= q0;elseclock_out <= q1;end if;elseclock_out <= '0';end if;end process output;end bhv;3： sel,分频器选择信号判断产生器 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sel isport(clock_in : in std_logic;Xnumber : in std_logic_vector(3 downto 0); sel_out : out std_logic);end entity;architecture bhv of sel issignal XsubTen : std_logic_vector(3 downto 0); signal q : std_logic_vector(4 downto 0);beginXsubTen <= 10 - Xnumber; sel: process(clock_in, q) beginif (clock_in'event and clock_in = '0') then if q + XsubTen >= 10 thenq <= q + XsubTen - 10;elseq <= q + XsubTen;end if;end if;if q >= Xnumber then sel_out <= '0';elsesel_out <= '1'; end if;end process sel;end bhv;4： mux2_1, 2 选 1 数据选择器 library ieee;use ieee.std_logic_1164.all;entity mux_21 is port(a : in std_logic; b : in std_logic; s : in std_logic;y : out std_logic );end entity;architecture bhv of mux_21 isbeginwith s selecty <= a when '1' ,b when others;end bhv;5： number,分频器系数处理器 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity number isport( n : in std_logic_vector(3 downto 0);number0 : out std_logic_vector(3 downto 0); number1 : out std_logic_vector(3 downto 0));end entity;architecture bhv of number is beginnumber0 <= n; number1 <= n+1;end bhv;。