EDA实验报告数字钟.doc

®南昌大学卖验掖告学生姓名： 刘光林 学 号：6100209064 专业班级：卓越（3+1 ）实验类型：□验证□综合■设计□创新 实验日期： 实验成绩：实验四多功能数字钟设计—x实验设计1、 数字显示当前的小时、分钟；2、 闹钟和24小时计时显示；3、 一个调节键，用于调节目标数位的数字对调节的内容敏感，如调节分钟或 秒时，保持按下时自动计数，否则以脉冲计数；4、 一个功能键，用于切换不同状态：计时、调时、调分、调秒二实验步骤根据实验要求可以将该工程设计几个模块：1、秒计时模块代码：11brary ieee;use ieee. std_logic_1164. all;use icee. std_logic_unsigncd. al 1;entity second isport (elk,reset,setmin:in std_logic;enmin:out std_logic;sout:out std_logic_vector (7 downto 0));end second;architecture bhv of second issignal count:std logic vector(7 downto 0);signal enmini, enmin2:std_logic;beginsout〈二count;enmin2<=(setmin and elk);enmin<=(enminl or enmin2);process (elk, reset, setmin)beginif reset二'O' then count〈二〃00000000";elsif elk'event and elk二'1’ thenif count (3 downto 0)=〃1001" thenif count<16#60# thenif count二"01011001" thenenminl<=， T ;count〈二"00000000";else count〈二count+7;end if;else count〈二〃00000000";end if;elsif count<16#60# thencount〈二count+1;enmini <=，O';else count<=/z00000000，z;end if;end if;end process;end bhv;其中,CLK是时钟信号,RESET是复位信号,SETMTN为分钟设置信号,ENMTN作为 下一模块分钟设计的时钟信号,sout输岀信号最后接在动态译管码芯片上，得 出实验要求的秒显示。

2、分计时模块代码：library ieee;use ieee.std_logic_l164. al l;use ieee.std logic unsigned.all;entity minute isport (elk, enmin, reset, sethour:in std logic;enhour,speak:out std_logic;mout:out std logic vector (7 downto 0)); encl minute;architecture bhv of minute issignal count:std_logic_vector(7 downto 0);signal enhourl,cnhour2:stdlogic;beginmout〈二count;enhour2<= (sethour and elk);enhour<=(enhourl or enhour2);process (elk,reset, sethour)beginif reset二'O' thencount<=/zOOOOOOOOz，;elsif enmin'event and enmin二i thenif count(3 downto 0)="1001〃 thenif count<16#60# thenif count二"01011001" thenenhourl<=， T ;count〈二"00000000〃；else count<=count+7;end if;else count〈="00000000";end if;elsif count<16#60# thencount<=count+l;enhourl<=，O';else count〈二"00000000";end if;end if;if count二"00000000〃 thenspeak<=， r ;else speak<=, O';encl if;end process;encl bhv;其中,CLK接秒模块中的ENM1N信号,RESET同样是复位信号,ENHOUR作为下 一模块小时的时钟信号,mout输出信号最后接在动态译码管芯片上.得出实验 要求得分显示，sehour为调时信号。

3、小时模块代码：library ieee;use ieee・std logic 1164. all;use ieee.std_logic_unsigned, all;entity hour isport (enhour,reset:in std_logic;hout:out stdlogicvector(7 downto 0));end hour;architecture bhv of hour issignal count:std_logic_vector(7 downto 0);beginhout〈二count;process (enhour, reset)beginif reset二'O' thencount"”00000000〃；elsif enhour"event and enhour二'1’ thenif count(3 downto 0)="1001〃 thenif count<16#23# thencount〈二count+7;else count〈二"00000000”；end if;elsif count<16#23# thencount〈二count+1;else count〈二〃00000000";end if;end if;end process;end bhv;4、闹钟功能模块代码：library ieee;use ieee.std_logic_l164. al l;use ieee. std_logic_unsigned, all;entity clock isport (elk:in std logic;setclk:in std_logic_vector(1 downto 0);hour, minute:in std logic vector (7 downto 0);minute1,hourl:buffer std_logic_vector(7 downto 0); co:out stdlogic);end clock;architocture bhv of clock issignal count 1,count2:std_logic_vector(7 downto 0); beginminutel<=countl;hourl<=count2;process (elk, setelk)beginif elk'event and elk二T' thenif setclk二"01" thenif count 1(3 downto 0)="1001" thenif countl<16#60# thenif countl二"01011001" thencount 1〈二〃00000000〃；else countl<=countl+7;end if;else count 1〈二"00000000";end if;elsif countl<16#60# thencountl<=count1+1;else countl〈二"00000000";end if;elsif setclk二"10" thenif count2 (3 downto 0)="1001" thenif count2<16#23# then count2<=count2+7;else count2<="00000000";end if;elsif count2<16#23# thencount2<=count2+l;else count2〈二"00000000";end if;end if;end if;if hourl=hour thenif minutel二minute thenco〈二'r ；el se co<=，0，;end if;el se co<=，O';end if;end process;end bhv;5、时间和闹钟时间(动态数码管)显示模块代码：library ieee;use ieee・std logic 1164. all;use ieee. std_logic_unsigned. all;entity scan isport (elk,reset:in std_logic;set elk: stcl logic vec to r (1 downto 0);second, minute, hour, minutel, hourl: in std_logic_vector (7 clownto 0);cout:out stdlogicvector(3 downto 0);c:out std_logic_vector(7 downto 0);sol:out stdlogicvector(2 downto 0));end scan;architecture bhv of sean issignal count:std_logic_vector(2 clownto 0);signal dout:std_logic_vector(3 downto 0); beginsei〈二count;process (elk,reset, setclk)beginif reset二‘0’ thencount〈二〃000〃;elsif elk'event and clk=， T then if count〉二"101" thencount〈二〃000〃；elsecount〈二count+1;end if;end if;if setclk二〃00〃 thencasecountiswhen〃101〃=>dout<=second (3downto0);when〃100〃二〉dout〈二second (7downto4);whe n011〃=>dout<=minute(3downlo0);when〃010〃二〉clout〈二 minute (7downto4);when001=>dout<=hour(3 downto 0);when〃000〃=>dout<=hour(7 downto 4);。