180纳米工艺嵌入式每单元存储双比特数据的闪存程序存储器设计.pdf

上海交通大学 硕士学位论文 180纳米工艺嵌入式每单元存储双比特数据的闪存程序存储器设 计 姓名：李强 申请学位级别：硕士 专业：电子与通信工程 指导教师：李翔;唐伟 20060701 申请上海交通大学工程硕士论文 I 180 纳米工艺嵌入式 每单元存储双比特数据的闪存程序存储器设计 180 纳米工艺嵌入式 每单元存储双比特数据的闪存程序存储器设计 摘摘 要要 最早出现于 20 世纪 60 年代的半导体存储器件现如今在半导体器 件市场占有相当大的比重，它们被广泛的应用于计算机、通讯、交通、 航天等领域Flash Memory（快闪存储器[1] ）作为现如今最成熟的非挥 发性半导体存储器已成为应用最广泛的存储器之一它以其高密度、非 挥发、擦写易实现等诸多独特的优点在存储器市场中占据重要的地位 随着半导体制造工艺技术的不断进步，快闪存储器芯片内存储单元 的制造尺寸大幅缩小，集成度显著提高，有效满足了市场对大容量存储 器芯片的需求目前，180 纳米的工艺正被广泛应用于各种快闪存储器 芯片的设计和制造 为了更有效地降低快闪存储器的成本，提高容量，一种新型的快闪 存储器技术应运而生它不同于以往的一个存储单元只能保存一个比特 数据的传统存储器，而是实现了每个物理存储单元可以存储两个甚至多 个比特数据，大大提高了存储器的密度，也就是相当于用现如今流行的 存储器的一半的芯片面积就可以获得相同的存储容量。

近几年来，随着 SOC(片上系统[2])的兴起，嵌入式快闪存储器正得 到长足的发展和广泛的应用本文阐述的就是 180 纳米工艺每单元可存 储两个比特数据的应用于 ARM 处理器芯片的嵌入式快闪存储器的设计 过程 首先，基于这种新型的每单元可存储两个比特数据的存储单元的特 点及其如何实现读、写、擦的操作过程，设计出实现这些操作的架构， 从而进行各个功能模块的划分和各项参数的设定 其次，存储单元阵列的设计是存储器产品设计中的核心内容本文 申请上海交通大学工程硕士论文 II 阐述了一种全新的阵列设计方法：根据存储单元的特点和客户的需求， 充分利用“扇区”[3]的概念，将存储器以扇区为单位进行分割，并靠全 局位线实现整个阵列的衔接和组合从而既满足了各项设计要求，又避 开了存储单元固有的缺点所带来的不利影响 再有，在存储器产品设计中，字线和位线的解码是除了阵列设计以 外最为重要的一部分，关系着整个产品的芯片面积和性能本文提出了 针对以往解码电路设计的改进方案，创新地采用了预解码与二次解码加 后级驱动的方式实现了字线的解码功能，大大压缩了面积，使得在 0.4 微米的高度内（每条字线所占的高度）实现字线解码电路的版图设计成 为可能，从而达成了字线的解码电路与字线间形成一一对应进行驱动的 效果，提高了字线的建立速度。

而对于位线解码电路的设计，本文借鉴 了字线的分级进行解码的方式，共分三级实现了解码功能，更是根据精 密的计算很好的控制了解码电路中的各个器件的尺寸，压缩了位线解码 电路的版图高度，从而即节省了面积，又能很好的满足各项要求 最后，状态机[4]是整个存储器芯片中的中央处理器本文采用同步 的时序控制方式设计了这一存储器中的核心部件，弥补了以往设计中较 难控制时序的缺陷，顺利的实现了存储器擦写过程的各个状态之间的转 换除此以外，还设计出数个功能更完备的标准单元，使状态机的设计 更加简洁，使得这一复杂的逻辑电路更易实现，更易查错，更易修改 关键字：关键字：快闪存储器，每单元双比特，字线，扇区，状态机 申请上海交通大学工程硕士论文 III 180NM PROCESS EMBEDDED ONE CELL TWO BIT CORE FLASH MEMORY DESIGN ABSTRACT The semiconductor memory was invented in 1960’s. Now the proportion of it is more and more larger in the semiconductor memory market. It is used in the field of computer, communication, traffic, space flight etc. widely. As we all know, Flash memory [1], as the most full-blown non-volatilization semiconductor memory, is used most widely. And it is very important in the memory market because of its high density, to be programmed and erased easily, non-volatilization etc. Along with the development of semiconductor fabrication technology, the area of the memory cell in flash memory chip is reduced, the integration is improved, then the flash memory can meet the demand of the market for large density. Now, 180ns is used in the fabrication of the flash memory widely. In order to reduce the cost of flash memory and improve the density, a new type of flash memory was invented. It is different with the traditional flash memory in which one flash memory cell only can save one bit data. It can save two or more than two bits data in one cell. So it enlarged the density of the memory. It can use the one half of memory chip area to save the same information now. Nowadays, along with the development of SOC [2], embedded flash memory is being developed and used widely. The thesis will descript how to design a embedded flash memory to meet the ARM processor’s requirement based on the new type flash memory cell which can save two bits data using 180ns process. First of all, based on the new type flash memory’s characterization and 申请上海交通大学工程硕士论文 IV the progress how to fulfill the read, program and erase, to design the architecture of the three operations to decide the division and specification of every function element. Secondly, the design of flash memory array is the most important work in the design of memory. And it is the key factor whether the design is successful or not. Based on the characterization of the cell and customer’s requirement, to use the idea about sector [3] well to separate the array to several sector and integrate the sectors use the global bit lines so that the design can meet all of the specification and this avoid the effect because of the cell’s inherent defect. Besides of this, the design of the word and bit lines’ decoder is the most important except array design. It affects the area and performance of the whole chip. Improving the design of the old decoder innovatively, to adopt the pre-decoder, the second decoder and the final driver to decode the word lines of the array so that the layout area of decoder is reduced. Then the height of the decoder’s layout is less than 0.4um so that every word line can be drive by one driver and the setup time of word line is reduced. Improving the design of bit line’s decoder, to adopt the hierarchical decoder following the word lines’ decoder, to separate the bit lines decoder to 3 levels and reduced the MOS size in the bit lines’ decoder based on the close calculation. The layout area of bit lines’ decoder is reduced again. The set up time and the voltage loss on it meet the specification. Finally, state machine [4] is the CPU of the whole memory. To adopt the synchronous clock to design the core, it makes up the bug that the timing is not controlled easily in the old design and can transfer the states in the program and erase flow. Except this, to design several standard cells, it make the design, debug, and modi。