H.264AVC中自适应去块效应滤波的硬件架构设计与实现.pdf

上海交通大学硕士学位论文H.264/AVC中自适应去块效应滤波的硬件架构设计与实现摘 要H.264/AVC 是 ITU-T Video Coding Experts GroupVCEG与ISO/IEC Moving Picture Experts Group MPEG 共同组成的 Joint VideoTeamJVT所制定的最新一代视频编码国际标准,是目前图像通信研究领域的热点问题之一H.264/AVC 新标准中采用了大量新工具在编码效率上大大提高是 MPEG-2 标准的两倍左右但其运算复杂度也大为增加再加上实际应用环境中实时运算的限制它对硬件实现提出了巨大的挑战本文致力于提出一种应用于 H.264/AVC标准的自适应去块效率滤波器的硬件架构设计并给出了架构的具体实现本文首先介绍了视频压缩标准的发展和用到的关键技术新标准 H.264/AVC 的概貌和新特点以及 H.264 标准中去块效应滤波的要求然后分析目前已有的一些视频解码系统提出 H.264/AVC 解码系统结构对去块效应模块设计的要求并结合编解码环中去块模块的位置相同性对去块效应模块计算复杂度进行了分析本文对环内滤波和后处理滤波特点进行了比较详细分析了H.264/AVC 中去块效应滤波的多层次自适应性特点滤波确定过程上海交通大学硕士学位论文和各种滤波器的计算过程在算法分析的基础上结合硬件架构设计的要求在滤波顺序滤波数据结构和存储结构上对去块效应滤波算法进行优化为硬件架构的提出奠定了算法基础本文提出了一种可用于不同编解码器系统结构的并行去块效应滤波器根据 44 像素块之间数据的依赖关系合理组织数据存放顺序并利用本地存储器降低对系统总线带宽的需求通过合理配置存储器存储结构的方法实现垂直和水平两个方向的滤波操作从而提高运算速度详细设计了标准滤波器和强滤波器的硬件架构宏块参数的处理和滤波操作采用并行处理方式当前宏块滤波的间隙可以读取下一个宏块的参数计算其滤波强度值可以大大减少宏块滤波时钟周期在此基础上分析了不同码流宏块滤波分布情况有些码流宏块不滤波的情况占有非常大比例根据滤波强度值提出八种滤波模式控制整个滤波数据流的操作可以大大提高数据访问效率该处理器除了运算速度快之外还可以节省 50的总线带宽在本文提出的硬件架构的基础上对整个架构用硬件描述语言进行实现分析功能模块的处理速度和性能并对总体设计进行性能分析通过仿真分析可以看出一个宏块去块效应滤波仅需要 270个周期在 0.18m 工艺下最大频率 200M 时综合逻辑门数为136.2K满足高清图像的实时解码要求上海交通大学硕士学位论文关键词H.264/AVC编码器解码器去块效应滤波环路滤波硬件架构上海交通大学硕士学位论文HARDWARE ARCHITECTURES DESIGN ANDIMPLEMENT OF ADAPTIVE DEBLOCKING FORH.264/AVCABSTRACTH.264/AVC is a new video coding international standard proposedby Joint Video Team (JVT), which organized by the ITU-T Video CodingExperts Group (VCEG) and the ISO/IEC Moving Picture Experts Group(MPEG). In order to achieve high compressing gain, some complicatedtools are introduced in the new standard. Although the coding efficiencyof the H.264/AVC is as two times better than that of MPEG-2, for somereal-time applications, the complicated computational characteristics willlead great challenges for today’s VLSI implementation. In this paper, wepropose a VLSI architecture design of adaptive deblocking filter forH.264/AVC.In this thesis, the development history and critical technology ofH.264/AVC standard is briefly introduced firstly, Then the model of videodecoder system are demonstrated. Furthermore, after the introduction ofthe H.264/AVC encoder or decoder system research both in and abroad,the computational complexities of adaptive daglocking filter areanalyzed.上海交通大学硕士学位论文Loop filter and post filter are compared. The several adaptivefilterthe determination of boundary strength and filter computation ofdeblocking filter in H.264/AVC are analyzed. Based on the analysis ofalgorism and considered of the require of VLSI design, the algorism ofdeblocking filter are optimized in filter order, data structure and memoryprocess. The optimal algorism is the base of hardware architecture.This thesis presents an implemented VLSI architecture for adaptivedeblocking loop filter in H.264/AVC. In this architecture, data access iscarefully organized and some other measures are adopted, which increasethe efficiency of getting data from the local SRAM and highly reduce thetotal cycles of filtering process. This design supports both horizontalfiltering and vertical filtering on the same circuit. The architecture ofstandard filter and strong filter are design. The macroblock parameter andfilter process is parallel implemented in design. When current macroblockdata are filtered, the next macroblock parameters are read and boundarystrength values are computed. In this way, the process clock cyclesdecreased. According to boundary strengths, the filter mode is putforward. The memory access can be decided by filter mode. Thisarchitecture design can save 50 present bus bands, excepting the highspeed in process.In the last part, the architecture design of deblocking filter isimplementing in verilog language. Simulation show that only 270 clock上海交通大学硕士学位论文cycles are needed to finish filtering a macroblock for deblocking filter,and the synthesized logic gate count is only 136.2K under 0.18mtechnology when maximum frequency is 200 MHz. It can process HDvideo in time.Key Words: H.264/AVC, encoder, decoder, deblocking filter, loop filter,hardware architecture, VLSI上海交通大学硕士学位论文- I -图例索引图 1 - 1 视频编码标准的发展.....................................................................................1 图 1-2 H . 2 6 4 编码器框图 ..........................................................................................5 图 1 - 3 空间预测模式...............................................................................................7 图 1-4 系数扫描顺序a 帧格式 b 场格式.........................................................7 图 1-5 C A B A C 编码器基本框图 ...................................................................................8 图 2-1 近几年视频压缩标准实现方法的演进 ............................................................ 14 图 2-2 解码器结构图............................................................................................... 15 图 2-3 H . 2 6 4 / A V C 解码系统的架构模型 ................................................................... 15 图 2-4 H . 2 6 4 / A V C 系统编码流程图 .......................................................................... 16 图 2-5 H . 2 6 4 / A V C 系统解码流程图 .........。