现代CMOS工艺基本流程ppt课件.ppt

现代代CMOS工工艺根本流程根本流程现代CMOS工艺根本流程Silicon Substrate P+~2um~725umSilicon Epi Layer P−选择衬底•晶圆的选择•掺杂类型〔N或P〕•电阻率〔掺杂浓度〕•晶向•高掺杂(P+)的Si晶圆•低掺杂(P−)的Si外延层Silicon Substrate P+Silicon Epi Layer P− Pad Oxide热氧化•热氧化•构成一个SiO2薄层，厚度约20nm•高温，H2O或O2气氛•缓解后续步骤构成的Si3N4对Si衬底呵斥的应力Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideSi3N4淀积•Si3N4淀积•厚度约250nm•化学气相淀积(CVD)•作为后续CMP的停顿层Silicon Substrate P+Silicon Epi Layer P-Silicon NitridePhotoresist光刻胶成形•光刻胶成形•厚度约0.5~1.0um•光刻胶涂敷、曝光和显影•用于隔离浅槽的定义Silicon Substrate P+Silicon Epi Layer P-Silicon NitridePhotoresistSi3N4和SiO2刻蚀•Si3N4和SiO2刻蚀•基于氟的反响离子刻蚀(RIE)Silicon Substrate P+Silicon Epi Layer P-Silicon NitridePhotoresistTransistor Active AreasIsolation Trenches隔离浅槽刻蚀•隔离浅槽刻蚀•基于氟的反响离子刻蚀(RIE)•定义晶体管有源区Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideTransistor Active AreasIsolation Trenches除去光刻胶•除去光刻胶•氧等离子体去胶，把光刻胶成分氧化为气体Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideFuture PMOS TransistorSilicon DioxideFuture NMOS TransistorNo current can flow through here!SiO2淀积•SiO2淀积•用氧化物填充隔离浅槽•厚度约为0.5~1.0um，和浅槽深度和几何外形有关•化学气相淀积(CVD)Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideFuture PMOS TransistorFuture NMOS TransistorNo current can flow through here!化学机械抛光•化学机械抛光(CMP)•CMP除去外表的氧化层•到Si3N4层为止Silicon Substrate P+Silicon Epi Layer P-Future PMOS TransistorFuture NMOS Transistor除去Si3N4•除去Si3N4•热磷酸(H3PO4)湿法刻蚀，约180℃Trench OxideCross SectionBare Silicon平面视图•完成浅槽隔离(STI)Silicon Substrate P+Silicon Epi Layer P-Future PMOS TransistorFuture NMOS TransistorPhotoresist光刻胶成形•光刻胶成形•厚度比较厚，用于阻挠离子注入•用于N-阱的定义Silicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorPhotoresistN- WellPhosphorous (-) Ions磷离子注入•磷离子注入•高能磷离子注入•构成部分N型区域，用于制造PMOS管Silicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorN- Well除去光刻胶PhotoresistSilicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorN- Well光刻胶成形•光刻胶成形•厚度比较厚，用于阻挠离子注入•用于P-阱的定义Silicon Substrate P+Silicon Epi Layer P-PhotoresistN- WellBoron (+) IonsP- Well•硼离子注入•高能硼离子注入•构成部分P型区域，用于制造NMOS管硼离子注入Silicon Substrate P+Silicon Epi Layer P-N- WellP- Well除去光刻胶Silicon Substrate P+Silicon Epi Layer P-P- WellN- Well退火•退火•在600~1000℃的H2环境中加热•修复离子注入呵斥的Si外表晶体损伤•注入杂质的电激活•同时会呵斥杂质的进一步分散•快速加热工艺(RTP)可以减少杂质的分散Trench OxideN- WellP- WellCross Section•完成N-阱和P-阱平面视图Silicon Substrate P+Silicon Epi Layer P-P- WellN- Well Sacrificial Oxide牺牲氧化层生长牺牲氧化层生长•牺牲氧化层生长•厚度约25nm•用来捕获Si外表的缺陷Silicon Substrate P+Silicon Epi Layer P-P- WellN- Well除去牺牲氧化层•除去牺牲氧化层•HF溶液湿法刻蚀•剩下干净的Si外表Silicon Substrate P+Silicon Epi Layer P-P- WellN- Well Gate Oxide栅氧化层生长•栅氧化层生长•工艺中最关键的一步•厚度2~10nm•要求非常干净，厚度准确(±1Å)•用作晶体管的栅绝缘层Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellPolysilicon多晶硅淀积•多晶硅淀积•厚度150~300nm•化学气相淀积(CVD)Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellPhotoresistChannel LengthPolysilicon光刻胶成形•光刻胶成形•工艺中最关键的图形转移步骤•栅长的准确性是晶体管开关速度的首要决议要素•运用最先进的曝光技术——深紫外光(DUV)•光刻胶厚度比其他步骤薄Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellPhotoresistChannel Length多晶硅刻蚀•多晶硅刻蚀•基于氟的反响离子刻蚀(RIE)•必需准确的从光刻胶得到多晶硅的外形Silicon Substrate P+Silicon Epi Layer P-P- WellN- Well Gate Oxide Poly Gate Electrode除去光刻胶Trench OxideN- WellP- WellCross SectionPolysilicon平面视图•完成栅极Silicon Substrate P+Silicon Epi Layer P-P- WellN- Well Gate Oxide Poly Gate Electrode Poly Re-oxidation多晶硅氧化•多晶硅氧化•在多晶硅外表生长薄氧化层•用于缓冲隔离多晶硅和后续步骤构成的Si3N4Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellPhotoresist光刻胶成形•光刻胶成形•用于控制NMOS管的衔接注入Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellPhotoresistArsenic (-) IonsN TipNMOS管衔接注入•NMOS管衔接注入•低能量、浅深度、低掺杂的砷离子注入•衔接注入用于减弱栅区的热载流子效应Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN Tip除去光刻胶Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellPhotoresistN Tip光刻胶成形•光刻胶成形•用于控制PMOS管的衔接注入Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellPhotoresistBF2 (+) IonsN TipP Tip•PMOS管衔接注入•低能量、浅深度、低掺杂的BF2+离子注入•衔接注入用于减弱栅区的热载流子效应PMOS管衔接注入Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN TipP Tip除去光刻胶Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellSilicon NitrideThinner HereThicker HereN TipP TipP TipSi3N4淀积•Si3N4淀积•厚度120～180nm•CVDSilicon Substrate P+Silicon Epi Layer P-P- WellN- WellSpacer SidewallN TipP TipP TipSi3N4刻蚀•Si3N4刻蚀•程度外表的薄层Si3N4被刻蚀，留下隔离侧墙•侧墙准确定位晶体管源区和漏区的离子注入•RIESilicon Substrate P+Silicon Epi Layer P-P- WellN- WellPhotoresistN TipP Tip光刻胶成形•光刻胶成形•用于控制NMOS管的源/漏区注入Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellPhotoresistArsenic (-) IonsN+ DrainN+ SourceP TipNMOS管源/漏注入•NMOS管源/漏注入•浅深度、重掺杂的砷离子注入，构成了重掺杂的源/漏区•隔离侧墙阻挠了栅区附近的注入Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP Tip除去光刻胶Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourcePhotoresistP Tip光刻胶成形•光刻胶成形•用于控制PMOS管的源/漏区注入Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellBF2 (+) IonsPhotoresistN+ DrainN+ SourceP+ SourceP+ DrainPMOS管源/漏注入•PMOS管源/漏注入•浅深度、重掺杂的BF2+离子注入，构成了重掺杂的源/漏区•隔离侧墙阻挠了栅区附近的注入Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ SourceP+ DrainLightly Doped “Tips〞除去光刻胶和退火•除去光刻胶和退火•用RTP工艺，消除杂质在源/漏区的迁移Trench OxidePolysiliconCross SectionN- WellP- WellN+ Source/DrainP+ Source/DrainSpacer平面视图•完成晶体管源/漏极，电子器件构成Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ Source除去外表氧化物•除去外表氧化物•在HF溶液中快速浸泡，使栅、源、漏区的Si暴显露来Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceTitaniumTi淀积•Ti淀积•厚度20~40nm•溅射工艺•Ti淀积在整个晶圆外表Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceTitanium SilicideUnreacted TitaniumTiSi2构成•TiSi2构成•RTP工艺，N2气氛，800℃•在Ti和Si接触的区域，构成TiSi2•其他区域的Ti没有变化•称为自对准硅化物工艺(Salicide)Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceTitanium SilicideTi刻蚀•Ti刻蚀•NH4OH+H2O2湿法刻蚀•未参与反响的Ti被刻蚀•TiSi2保管下来，构成Si和金属之间的欧姆接触Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGBPSG淀积•硼磷硅玻璃(BPSG)淀积•CVD，厚度约1um•SiO2并掺杂少量硼和磷•改善薄膜的流动性和禁锢污染物的性能•这一层绝缘隔离器件和第一层金属Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGBPSG抛光•硼磷硅玻璃(BPSG)抛光•CMP•在BPSG层上获得一个光滑的外表Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGPhotoresist光刻胶成形•光刻胶成形•用于定义接触孔(Contacts)•这是一个关键的光刻步骤Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGPhotoresist接触孔刻蚀•接触孔刻蚀•基于氟的RIE•获得垂直的侧墙•提供金属和底层器件的衔接Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSG除去光刻胶Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGTitanium NitrideTiN淀积•TiN淀积•厚度约20nm•溅射工艺•有助于后续的钨层附着在氧化层上Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGTitanium NitrideTungsten钨淀积•钨淀积•CVD•厚度不少于接触孔直径的一半•填充接触孔Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact Plug钨抛光•钨抛光•CMP•除去外表的钨和TiN•留下钨塞填充接触孔Trench OxidePolysiliconCross SectionN- WellP- WellN+ Source/DrainP+ Source/DrainSpacerContact平面视图•完成接触孔，多晶硅上的接触孔没有出如今剖面图上Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1Ti (200Å) - electromigration shuntTiN (500Å) - diffusion barrierAl-Cu (5000Å) - main conductorTiN (500Å) - antireflective coatingMetal1淀积•第一层金属淀积(Metal1)•实践上由多个不同的层组成•溅射工艺Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1Photoresist光刻胶成形•光刻胶成形•用于定义Metal1互连Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1PhotoresistMetal1刻蚀•Metal1刻蚀•基于氯的RIE•由于Metal1由多层金属组成，所以需求多个刻蚀步骤Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1除去光刻胶Trench OxidePolysiliconCross SectionN- WellP- WellN+ Source/DrainP+ Source/DrainSpacerContactMetal1平面视图•完成第一层互连Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1IMD淀积•金属间绝缘体(IMD)淀积•未掺杂的SiO2•延续的CVD和刻蚀工艺，厚度约1um•填充在金属线之间，提供金属层之间的绝缘隔离Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1IMD抛光•IMD抛光•CMPSilicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1Photoresist光刻胶成形•光刻胶成形•用于定义通孔(Vias)Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1PhotoresistIMD1通孔刻蚀•通孔刻蚀•基于氟的RIE，获得垂直的侧墙•提供金属层之间的衔接Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1除去光刻胶TungstenSilicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1 W Via PlugTiN和钨淀积•TiN和钨淀积•同第一层互连Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1 W Via Plug钨和TiN抛光•钨和TiN抛光•同第一层互连Trench OxidePolysiliconCross SectionN- WellP- WellN+ Source/DrainP+ Source/DrainSpacerContactMetal1Via1平面视图•完成通孔Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1 W Via PlugMetal2Metal2淀积•Metal2淀积•类似于Metal1•厚度和宽度添加，衔接更长的间隔，承载更大的电流Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1PhotoresistIMD1 W Via PlugMetal2光刻胶成形•光刻胶成形•相邻的金属层连线方向垂直，减小层间的感应耦合Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1PhotoresistIMD1 W Via PlugMetal2Metal2刻蚀•Metal2刻蚀•类似于Metal1Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1 W Via PlugMetal2除去光刻胶Trench OxidePolysiliconCross SectionN- WellP- WellN+ Source/DrainP+ Source/DrainSpacerContactMetal1Via1Metal2平面视图•完成第二层互连，后面的剖面图将包括右上角的压焊点Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1 W Via PlugPassivationMetal2钝化层淀积•钝化层淀积•多种可选的钝化层，Si3N4、SiO2和聚酰亚胺等•维护电路免受刮擦、污染和受潮等Silicon Substrate P+Silicon Epi Layer P-P- WellN- WellN+ DrainN+ SourceP+ DrainP+ SourceBPSGW Contact PlugMetal1IMD1 W Via PlugPassivationBond PadPoly GateGate OxideSilicideSpacerMetal2钝化层成形•钝化层成形•压焊点翻开，提供外界对芯片的电接触Cross SectionTrench OxideN+ Source/DrainP+ Source/DrainSpacerContactMetal1PolysiliconVia1+5V SupplyVOUTN- WellP- WellMetal2GroundBond PadVIN平面视图•完成，显示了电气衔接和部分压焊点完成略有不同的另一个工艺流程Vth校正注入场氧化层TiN。