组合函数及相应电路

1、,Chapter 4,Click to edit Master title Style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,Chapter 3 Combinational,Logic Design II,Logic and Computer Design Fundamentals,Chapter 4,2,Overview,Functions and functional blocks,Rudimentary logic functions,Decoding,Encoding,Selecting,Chapter 4,3,Functions and Functional Blocks,The functions considered are those found to be very useful in design,Corresponding to each of the functions is a combinational circuit implem

2、entation called a,functional block,.,In the past,many functional blocks were implemented as SSI,MSI,and LSI circuits.,Today,they are often simply parts within a VLSI circuits.,Chapter 4,4,Rudimentary Logic Functions,Four elementary combinational logic functions,Value-Fixing:,F=0,or,F=1 ,no Boolean operator,Transferring:,F=X ,no Boolean operator,Inverting:,F=X ,involves one logic gate,Enabling:,F=X,EN or F=X+EN,involves one or two logic gates,The first three are functions of a single variable X,0

3、,1,F,=,0,F,=,1,(a),F,=,0,F,=,1,V,CC,or V,DD,(b),X,F,=,X,(c),X,F,=,X,(d),Table 4-1,Functions of one variable,X,F,=0,F,=X,F,=,F=1,0,1,0,0,0,1,1,0,1,1,X,Chapter 4,5,Multiple-bit Rudimentary Functions,Multi-bit Examples:,A wide line is used to representa,bus,which is a vector signal,In(b)of the example,F=(F,3,F,2,F,1,F,0,)is a bus.,The bus can be split into,individual bits,as shown in(b),Sets of bits,can be split from the bus as shown in(c)for bits 2 and 1 of F.,The sets of bits need not be continuo

4、us as shown in(d)for bits 3,1,and 0 of F.,F,(d),0,F,3,1,F,2,F,1,A,F,0,(a),0,1,A,1,2,3,4,F,0,(b),4,2:1,F(2:1),2,F,(c),4,3,1:0,F(3),F(1:0),3,A,A,Chapter 4,6,Enabling Function,Enabling,permits an input signal to pass through to an output,Disabling,blocks an input signal from passing through to an output,replacing it with a fixed value,The value on the output when it is disable can be Hi-Z(as for three-state buffers and transmission gates),0,or 1,When disabled,0 output,When disabled,1 output,See Ena

5、bling App in text,X,F,EN,(a),EN,X,F,(b),Chapter 4,7,Decoder,Decoding-the conversion of an,n,-bit input code to an,m,-bit output code with n,m,2,n,such that each valid code word produces a unique output code,Circuits that perform decoding are called,decoders,Variable Decoder,Display Decoder,Types,Chapter 4,8,Decoder,Controller,Whats the bit length of data?,？,0,1,2,3,4,5,6,7,Chapter 4,9,Decoder,A,B,C,Y,0,Y,1,Y,2,Y,3,Y,4,Y,5,Y,6,Y,7,0,0,0,1,0,0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,0,0,

6、0,1,1,0,0,0,1,0,0,0,0,1,0,0,0,0,0,0,1,0,0,0,1,0,1,0,0,0,0,0,1,0,0,1,1,0,0,0,0,0,0,0,1,0,1,1,1,0,0,0,0,0,0,0,1,Chapter 4,10,Decoder,Decoding-the conversion of an,n,-bit input code to an,m,-bit output code with n,m,2,n,such that each valid code word produces a unique output code,Decoders:,decoder with 2 input and 4 output,74LS139(2-to-4-Line Decoder),decoder with 3 input and 8 output,74LS138(3-to-8-Line Decoder),decoder with 4 input and 16 output,MC14514(4-to-16-Line Decoder),Chapter 4,11,1-to-2-L

7、ine Decoder,2-to-4-Line Decoder,Note that the 2-4-line made up of 2 1-to-2-line decoders and 4 AND gates.,Decoder Examples,A,1,0,0,1,1,A,0,0,1,0,1,D,0,1,0,0,0,D,1,0,1,0,0,D,2,0,0,1,0,D,3,0,0,0,1,(a),D,0,=,A,1,A,0,D,1,=,A,1,A,0,D,2,=,A,1,A,0,D,3,=,A,1,A,0,(b),A,1,A,0,A,D,0,D,1,0,1,0,1,0,1,(a),(b),D,1,=,A,A,D,0,=,A,Chapter 4,12,Decoder Expansion,Decider with n input can have 2,n,output.When n is large,the circuit is very complex.,General procedure:,Let,k=n,.,If,k,is even,divide,k,by,2,obtain,k/2,.

8、Use,2,k,AND gates driven by two decoders of output size,2,k/2,.If k is odd,obtain,(k+1)/2,and,(k-1)/2,.Use,2,k,AND gates driven by a decoder of output size,2,(k+1)/2,and a decoder of output size,2,(k-1)/2,.,For each decoder resulting from step,2,repeat step,2,with,k,equal to the values obtained in step,2,until,k=1,.For,k=1,use a 1-to-2 decoder.,Still valid when output 2,n,Chapter 4,13,Example:3-to-8-Line Decoder,3-to-8-Line Decoder,Construct directly,drive 8 3-input ANDs,Hierarchically,divide th

9、e input signals equally,2-to-4-Line decoder,1-to-2-Line decoder,2-to-4-Line Decoder,drive 4 2-input ANDs,divide the input signals equally,1-to-2-Line decoder,Chapter 4,14,Circuit of 3-to-8-Line Decoder,Result,Chapter 4,15,Example:7-to-128-Line Decoder,7-to-128-Line Decoder,128 7-input ANDs are needed if constructed directly,Hierarchically,level 1:,4,-to-16-Line Decoder,3,-to-8-Line Decoder,4-to-16-Line decoder,16 2-input ANDs,Level 2:,2 2-to-4-Line Decoder,Constructed by the known 3-to-8-Line De

10、coders and 2-to-4-Line Decoders,Chapter 4,16,In general,attach,m,-enabling circuits to the outputs,See truth table below for function,Note use of Xs to denote both 0 and 1,Combination containing two Xs represent four binary combinations,Alternatively,can be viewed as distributing value of signal EN to 1 of 4 outputs,In this case,called a,demultiplexer,Decoder with Enable,EN,A,1,A,0,D,0,D,1,D,2,D,3,(b),EN,A,1,A,0,D,0,D,1,D,2,D,3,0,1,1,1,1,X,0,0,1,1,X,0,1,0,1,0,1,0,0,0,0,0,1,0,0,0,0,0,1,0,0,0,0,0,

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