FPGA读写i2c_verilog--精选文档

1、timescale 1ns / 1ps/ Company: / Engineer:/ Create Date:/ Design Name: / Module Name: iic_top/ Project Name: / Target Device: / Tool versions: / Description:/ Dependencies:/ / Revision:/ Revision 0.01 - File Created/ Additional Comments:/ /module iic_com(clk,rst_n,sw1,sw2,scl,sda,dis_data);input clk;/ 50MHzinput rst_n;/复位信号，低有效input sw1,sw2;/按键1、2,(1按下执行写入操作，2按下执行读操作)output scl;/ 24C02的时钟端口inout sda;/ 24C02的数据端口output7:0 dis_data;/数码管显示的数据/-/按键检测reg sw1_r,sw2_r;/键值锁存寄存器，每20ms检测一次键值 reg19:0 cnt_20

2、ms;/20ms计数寄存器always (posedge clk or negedge rst_n)if(!rst_n) cnt_20ms = 20d0;else cnt_20ms = cnt_20ms+1b1;/不断计数always (posedge clk or negedge rst_n)if(!rst_n) beginsw1_r = 1b1;/键值寄存鞲次唬挥屑贪聪率奔刀嘉?sw2_r = 1b1;endelse if(cnt_20ms = 20hfffff) beginsw1_r = sw1;/按键1值锁存sw2_r = sw2;/按键2值锁存end/-/分频部分reg2:0 cnt;/ cnt=0:scl上升沿，cnt=1:scl高电平中间，cnt=2:scl下降沿，cnt=3:scl低电平中间reg8:0 cnt_delay;/500循环计数，产生iic所需要的时钟reg scl_r;/时钟脉冲寄存器always (posedge clk or negedge rst_n)if(!rst_n) cnt_delay = 9d0;else if(cnt_delay = 9d4

3、99) cnt_delay = 9d0;/计数到10us为scl的周期，即100KHzelse cnt_delay = cnt_delay+1b1;/时蛹剖?always (posedge clk or negedge rst_n) beginif(!rst_n) cnt = 3d5;else begincase (cnt_delay)9d124:cnt = 3d1;/cnt=1:scl高电平中间,用于数据采样9d249:cnt = 3d2;/cnt=2:scl下降沿9d374:cnt = 3d3;/cnt=3:scl低电平中间,用于数据变化9d499:cnt = 3d0;/cnt=0:scl上升沿default: cnt = 3d5;endcaseendenddefine SCL_POS(cnt=3d0)/cnt=0:scl上升沿define SCL_HIG(cnt=3d1)/cnt=1:scl高电平中间,用于数据采样define SCL_NEG(cnt=3d2)/cnt=2:scl下笛?define SCL_LOW(cnt=3d3)/cnt=3:scl偷缙街屑?用于数据变化alwa

4、ys (posedge clk or negedge rst_n)if(!rst_n) scl_r = 1b0;else if(cnt=3d0) scl_r = 1b1;/scl信号上升沿 else if(cnt=3d2) scl_r = 1b0;/scl信号下降沿assign scl = scl_r;/产生iic所需要的时钟/-/需要写入24C02的地址和数据defineDEVICE_READ8b1010_0001/被寻址器件地址（读操作）define DEVICE_WRITE8b1010_0000/被寻址器件地址（写操作）defineWRITE_DATA8b1101_0001/写入EEPROM的数据define BYTE_ADDR8b0000_0011/写入/读出EEPROM的地址寄存器reg7:0 db_r;/在IIC上传送的数据寄存器reg7:0 read_data;/读出EEPROM的数据寄存器/-/读、写时序parameter IDLE = 4d0;parameter START1 = 4d1;parameter ADD1 = 4d2;parameter ACK1 = 4d

5、3;parameter ADD2 = 4d4;parameter ACK2 = 4d5;parameter START2 = 4d6;parameter ADD3 = 4d7;parameter ACK3= 4d8;parameter DATA = 4d9;parameter ACK4= 4d10;parameter STOP1 = 4d11;parameter STOP2 = 4d12;reg3:0 cstate;/状态寄存器reg sda_r;/输出数据寄存器reg sda_link;/输出数据sda信号inout方向控莆?reg3:0 num;/always (posedge clk or negedge rst_n) beginif(!rst_n) begincstate = IDLE;sda_r = 1b1;sda_link = 1b0;num = 4d0;read_data = 8b0000_0000;endelse case (cstate)IDLE:beginsda_link = 1b1;/数据线sda为inputsda_r = 1b1;if(!sw1_r | !sw2

6、_r) begin/SW1,SW2键有一个被按下db_r = DEVICE_WRITE;/送器件地址（写操作）cstate = START1;endelse cstate = IDLE;/没有任何键被按下endSTART1: beginif(SCL_HIG) begin/scl为高电平期间sda_link = 1b1;/数据线sda为outputsda_r = 1b0;/拉低数据线sda，产生起始位信号cstate = ADD1;num = 4d0;/num计数清零endelse cstate = START1; /等待scl高电平中间位置到来endADD1:beginif(SCL_LOW) beginif(num = 4d8) beginnum = 4d0;/num计数清零sda_r = 1b1;sda_link = 1b0;/sda置为高阻态(input)cstate = ACK1;endelse begincstate = ADD1;num = num+1b1;case (num)4d0: sda_r = db_r7;4d1: sda_r = db_r6;4d2: sda_r = db_r5;4d3: sda_r = db_r4;4d4: sda_r = db_r3;4d5: sda_r = db_r2;4d6: sda_r = db_r1;4d7: sda_r = db_r0;default: ;endcase/sda_r = db_r4d7-num;/送器件地址，从高位开始endend/else if(SCL_POS) db_r = db_r6:0,1b0;/器件地址左移1bitelse cstate = ADD1;endACK1:beginif(/*!sda*/SCL_NEG) begin/注：24C01/02/04/08/16器件可以不考虑应答位cstate = ADD2;/从机响应信号db_r = BYTE_ADDR;/ 1地址endelse cstate = ACK1;/等待从机响应endADD2:beginif(SCL_LOW) begin

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