三菱ipm应用手册资料.pdf

D-070328-02 1 P. MITSUBISHI DIPMITSUBISHI DIPMITSUBISHI DIPMITSUBISHI DIP- - - -IPMIPMIPMIPM APPLICATION GUIDANCEAPPLICATION GUIDANCEAPPLICATION GUIDANCEAPPLICATION GUIDANCE Apr. 12, 2006 COMPANY PROPRIETARY NOT TO BE REPRODUCED OR DISCLOSED WITHOUT SPECIFIC WRITTEN PERMISSION OF MITSUBISHI ELECTRIC CORPORATION Mitsubishi Electric Corporation Power Device Works D-070328-02 2 P. What is in a DIPWhat is in a DIP- -IPM IPM ? ? HVIC Level Shift Gate Drive UV Prot. LVIC Gate Drive UV Prot. Overcurrent Prot. 3 Motor RSHUNT CPU 15V AC Line DIP-IPM • IGBT and FWDi – 3φ φ IGBT bridge (6 IGBTs (5) Recommended to insert a Zener diode between each pair of control supply terminals to prevent surge destruction. (6) Power GND and Control GND should be connected at only a point N1. (Don’t overlap these two GND lines.) Example of Large DIP Ver3 The long wiring of GND might generate noise on input and cause malfunction. DIP-IPM HVIC1 HVIC2 HVIC3 VCC IN COM VB HO VS VCC IN COM VB HO VS VCC IN COM VB HO VS VCC UN VN WN Fo GND CFO CIN VNO WOUT VOUT UOUT UN VN WN Fo VN1 VP1 VP VP1 WP VUFB UP VUFS VVFB VVFS VWFB VWFS VNC CFOCIN P U W N VP1 MCU C3 C3 C3 C3 15 Vline C4(CFO) M C5 R1 Shunt resistor N1 LVIC If this wiring is too long, short circuit might be caused. V 5V line If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. VPC C2 C1 C2 C1 C2 C1 C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22μ∼2μF R-category ceramic capacitor for noise filtering. (Note: The capacitance value depends on the PWM control used in the applied system.) (1) (2) (3) (4) (4) (5) (3) (6) (5) D-070328-02 4 P. Ver.3 Input Circuit UP､VP､WP DIP-IPM UN､VN､WN 1kΩ 1kΩ 2.5ｋ Ω(min.) 2.5ｋ Ω(min.) Gate Driver Gate Driver Level shift circuit MCU Input threshold voltage V2.62.32.1Vth(on) V2.11.40.8Vth(off) unitmaxtypmin ? A 2.5kΩ pull-down resistor is built in each input terminal, no need of external resistor. ? If RC noise filter is added to input line, since voltage drop generated on filter resistor, please make sure that the DIP-IPM input level satisfying the specified threshold voltage. ? Input signal wiring should be as short as possible (2～3cm) and not too thin. D-070328-02 5 P. Circuit parameter select:Circuit parameter select: ●The voltage drop ΔVDBin P-side maximum on-period should be able to fully charged in P-side minimum off-period or N-side minimum on-period. ●VDB should not drop down below 13.5V. (Generally, ΔVDB ≦1V for calculation). ●Calculation example Capacitance: C= IDB××T1／Δ／ΔVDB(T1: the max. on-pulse of P-side IGBT) Resistance: R= {(VD－－VDB)××T0} ／／(C×Δ×ΔVDB)(T0: the min. off-period of P-side IGBT) Bootstrap Diode: Breakdown Voltage 600V, Recovery time RC time constant + Internal time delay D-070328-02 12 P. Timing Chart of SCTiming Chart of SC Error output Fo SC reference voltage CR circuit time constant delay Sense voltage of the Shunt resistance Output current Ic(A) Internal IGBT gate Protection circuit state N-side control input SC RESET SET Specific period ●Only N-side IGBTs shut down in case of SC ●The Fo output time has some difference by each DIP-IPM series. For more information, please refer each datasheet. All N-side IGBT shut down D-070328-02 13 P. UV:Under Voltage ProtectionUV:Under Voltage Protection COM VS Fo WN VN UN VNC VN1 DIP-IPM UOUT VOUT WOUT GND Fo WN VN UN VCC CIN W V U P WP VP UP IGBT1 Di1 IGBT2 Di2 IGBT3 Di3 IGBT4 Di4 IGBT5 Di5 IGBT6 Di6 N VPC HO IN VB VP1 VCC HO IN VS HO IN VS Input signal conditioning Gate drive Fo logic Protection circuit(SC) Control supply Under-Voltage protection (UV) LVIC CFO VVFBVB VVFS VWFBVB VWFS COM COM VUFB VUFS HVIC Input signal conditioning Level Shift Gate drive Control supply Under-Voltage protection (UV) VP1 VCC Same above VP1 VCC Same above High side UV for 15V supply High side gate driving part Low side UV for 15V supply for Low side gate driving part and control part 15V GND 15V GND 15V GND 15V GND D-070328-02 14 P. Timing Chart of UVTiming Chart of UV Error output Fo Output current Ic(A) Control supply voltage VD Protection circuit state Control input a7 a1 a2 a4 a6 a3 RESET UVD t UVD r SET RESET Keeping high-level output a5 Error output Fo Output current Ic(A) Control supply voltage VDB Protection circuit state Control input a6 a1 a2 a4 a5 a3 RESET UVDB t UVDB r SET RESET Keeping high-level output (No Fo output) (a) Low-side UV protection timing chart (b) High-side UV protection timing chart All Low-side IGBT gates are locked with Fo output IGBT gate is locked without Fo output Under Voltage Protection operation has some difference between each DIP series Please refer each datasheets. D-070328-02 15 P. OT:Over Temperature protectionOT:Over Temperature protection(Super mini DIP (Super mini DIP VerVer.4 only).4 only) Feature: ?This function detect LVIC temperature(not IGBT junction temp.) ?Purpose of this protection is detecting abnormal increase of case temp. It will be caused by cooling fun stops or loose fixing of heat 。