P1010rdb新单板u.docx

P1010rdb新单板u; 新单板P1010rdb的u-boot移植讲解 一、yocto project的建立1. 搭建linux环境，ubuntu 12.04 2. QorIQ SDK 1.7 Documentation〔1〕SDK 简介参考freescale的网站www.freescale /infocenter/index.jsp《topic=/QORIQSDK/2880375.html〔2〕安装SDK1. Mount the ISO on your machine:$ sudo mount -o loop QorIQ-SDK----yocto.iso /mnt/cdrom2. As a non-root user, install Yocto Project:$ /mnt/cdrom/install3. When you are prompted to input the install path, ensure that the current user has thecorrect permission for the install path. 〔3〕配置sdk的环境1、$ cd 2、$ ./scripts/host-prepare.sh 3、安装python-2.7.6, export PATH=/opt/python-2.7.6/bin:$PATH4、建立p1010rdb的开发环境：$ source ./fsl-setup-poky -m p1010rdb 将生产build_p1010rdb_release的目录，用于p1010rdb相关的开发，包括u-boot, kernel,rootfs等〔4〕编译工具链1、$ cd /build_p1010rdb_release/ 《《《《《《《《《《《《《《《《《、 $ bitbake fsl-toolchain〔5〕编译u-boot1、获取u-boot源码 $ bitbake -c patch u-boot2、修改u-boot代码，u-boot代码放在路径下，获取的办法$ bitbake -e | grep ^S= to get value of .3、修改编译u-boot的配置文件meta-fsl-ppc/conf/machine/p1010rdb.conf 主要是UBOOT_MACHINES = \的宏变量，这个变量的值决定了编译出来的u-boot的值。

4、编译《$ cd build__release 《$ bitbake -c compile -f u-boot 《$ bitbake u-bootNote: U-Boot image can be found inbuild__release/tmp/deploy/images// 5、去除《$ bitbake -c cleansstate u-boot二、P1010RDB启动必备知识1、内存映射 〔1〕Configuration, control, and status registers〔CCSR〕默认的CCSRBAR的地址为0x0_FF70_0000 可以被修改，修改CCSRBAR的地址为0x0_FF70_0000，即它自身地址 〔2〕Local access windows(LAW)a、P1010rdb定义了12个LAW, Each of these windows maps a programmable 4-Kbyte to 32-Gbyte region of the local36-bit address space to a specified target interface, such as the DDR controller, integrated flash controller, PCI Express controllers, or other targets.b、If two or more LAWs overlap, the lower numbered window takes precedence.For instance, consider two LAWs, set up as shown in the table below.c、Each LAW is defined by a base address register which specifies the starting address for the window, and an attribute register which specifies whether the mapping is enabled, the size of the window, and the target interface for that window.The LAW registers are accessed by reading and writing to an address comprised of the base address(specified in the CCSRBAR)LAW_LAWBAR0和LAW_LAWBAR1〔3〕Address translation and mapping units〔ATMU〕To facilitate flexibility in defining the address maps for external interfaces such as PCIExpress, the device provides ATMUs.The following types of translation and mapping operations are performed by the ATMUs:《 Translating the local 36-bit address to an external address space 《 Translating external addresses to the local 36-bit address space 《 Assigning attributes to transactions《 Mapping a local address to a target interface2、Reset, Clocking, and Initialization〔1〕Reset memory map/register definitiona. CCSRBARThe set of configuration, control, and status registers occupies a 1-Mbyte region ofmemory. Their location is programmable using the CCSR base address register(CCSRBAR). The default base address for the configuration, control, and status registersis 0x0_FF70_0000 (CCSRBAR = 0x000F_F700). CCSRBAR itself is part of the localaccess block of CCSR memory, which begins at offset 0x0 from CCSRBAR. BecauseCCSRBAR is at offset 0x0 from the beginning of the local access registers, CCSRBARalways points to itself. The contents of CCSRBAR are broadcast internally in the deviceto all functional units that need to be able to identify or create configuration transactions.b. Boot pageWhen e500 core comes out of reset, its MMU has one 4-Kbyte page defined at 0x0_FFFF_Fnnn. The core begins execution with the instruction at effective address 0x0_FFFF_FFFC. To get this instruction, the core's first instruction fetch is a burst read of boot code from effective address 0x0_FFFF_FFE0.〔2〕Power-on reset sequence(POR) The device defines the default boot ROM address range to be 8 Mbytes at address 0x0_FF80_0000 to 0x0_FFFF_FFFF. 。