基于veriloghdl的通行时间可变的交通灯控制器.docx

通行时间可变的交通灯控制器设计module tr1(ng,clk,reset,resets,emergency,lighta,lightb,seg,select);input ng,clk,reset,emergency,resets;output[6:0]seg;//显示用的output[3:0] lighta,lightb;//a 是主干道，b 是支干道output [3:0] select;//选择那一个管子进行显示reg clk1,clk2;//clk1 要 5HZ clk2 要几千 HZreg [3:0] select;reg tim1,tim2;//这是看你的等有没有变过颜色的控制信号reg [1:0] cont;reg[2:0]state1,state2,ste;两个控制颜色变化状态的信号reg[3:0]lighta,lightb;//a 是主干道，b 是支干道reg[3:0]num;//译码器是根据这个东西来译码的reg [35:0] fout;reg[6:0]seg;//显示reg[7:0] numa,numb;reg[7:0] red1,red2,green1,green2,yellow1,yellow2,left1,left2;always @(ng )if(!ng)begin //设置计数初值green1 0)if(numa[3:0]==0) beginnuma[3:0]0)if(numb[3:0]==0) beginnumb[3:0]<=4'b1001;numb[7:4]<=numb[7:4]-1;endelse numb[3:0]<=numb[3:0]-1;if(numb==1) tim2<=0;endendelse begintim2<=0;state2<=0;lightb<=4'b0100;end end always @(posedge clk2)begin //数码管扫描if(resets)begincont=0;select=4'b1111;;endelse begincase(cont)2'b00:begin num<=numa[3:0]; select<=4'b1101;cont<=cont+1; end2'b01:begin num<=numa[7:4]; select<=4'b1011;cont<=cont+1; end2'b10:begin num<=numb[3:0]; select<=4'b0111;cont<=cont+1; end2'b11:begin num<=numb[7:4]; select<=4'b1110;cont<=cont+1; endendcaseendendalways @(posedge clk2)begin //数码管译码显示case(num)4'b0000: seg<=7'b0111111; //04'b0001: seg<=7'b0000110; //14'b0010: seg<=7'b1011011; //24'b0011: seg<=7'b1001111; //34'b0100: seg<=7'b1100110; //44'b0101: seg<=7'b1101101; //54'b0110: seg<=7'b1111101; //64'b0111: seg<=7'b0000111; //74'b1000: seg<=7'b1111111; //84'b1001: seg<=7'b1101111; //9default: seg<=7'b0111111; //0endcaseendendmodule。