a10b500msscmosdacin0.6mm.pdf

1948IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998A 10-b, 500-MSample/s CMOS DAC in 0.6 mmChi-Hung Lin and Klaas BultAbstract— A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from dc to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from dc to Nyquist. The measured differential nonlinearity and integral nonlinear-ity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-?m, single-poly, four-metal, 3.3- V, standard digital CMOS process and occupies 0.6 mm?. When operating at 500 MSample/s, it dissipates 125 mW from a 3.3-V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry.Index Terms—CMOS analog integrated circuits, digital–analog conversion, matching, mixed analog–digital integrated circuits.I. INTRODUCTION THE pressure to reduce cost in mass market communi- cation devices such as cable modems and digital cable set-top boxes has created a need for embedded high-speed high-resolution digital-to-analog converters (DAC’s). With the ability to integrate analog circuits with memory and digital signal processing (DSP) circuits on the same die, CMOS tech- nology is poised to meet that challenge. In the past 20 years, much research has been devoted to DAC’s [1]–[8] optimized for time domain applications, such as high-resolution displaysfor computer graphics and high definition television (HDTV). These DAC’s were mainly focused on dc linearity, settling behavior, and glitch energy performance. When used to syn- thesize sinewaves in frequency-domain applications, however, their spurious free dynamic range (SFDR) performance istypically not sufficient for broad-band applications.As an example, a simplified architecture of a cable modem headend transmitter is shown in Fig. 1. The cable modem system consists of multiple channels, where each channel con- tains a digital modulator and a DAC. The channels can have different digital modulation schemes, for example, quadrature amplitude modulation (QAM) or quadrature phase-shift keying (QPSK). Without a high-speed, high-resolution DAC, these modulation functions must be implemented in the analog domain, which generally results in relatively poor quality signals. When multiple channels are combined simultaneously, it is very important that the DAC’s meet a minimum SFDR, or signals in one channel will be corrupted by spurious com-Manuscript received June 25, 1998; revised August 19, 1998. The authors are with the Broadcom Corporation, Irvine, CA 92618 USA (e-mail: chlin@, bult@).Publisher Item Identifier S 0018-9200(98)08566-7.ponents from other channels. Therefore, the major challenge for designing DAC’s for frequency domain applications is to obtain large wideband SFDR. Fig. 2 shows an example of a 16-QAM spectrum for cable modem upstream signals. The transmitted signal frequencies range from 5–65 MHz. Thespecification of the multimedia cable network system (MCNS) requires the (aliased) harmonics to be at least 47 dB below the fundamental signal. Experimental results have shown that this number translates into an SFDR of more than 52 dB for asingle tone sinewave. That is a difficult requirement to meet for DAC’s operating at high signal frequencies. The goal of the DAC reported here is to obtain true 10-bit performance (SFDR60 dB) for signals from dc to Nyquist, for sampling speeds up to 200 MSample/s. For embedded applications, use of standard digital CMOS processes and a small chip area is a must. The chip area of this DAC is 0.6 mmin a 0.35m, single-poly, four-metal, 3.3 V, standard digital CMOS process. Sections II and III discuss the advantages and shortcomings of binary-weighted DAC’s and thermometer-coded DAC’s, re- spectively. Section IV compares the area requirement for these binary-weighted and thermometer-coded DAC’s. Section V deals with the optimization of the architecture for minimum area. Section VI shows circuit implementation and layout issues. Section VII presents results from measurements, and Section VIII summarizes the conclusions.II. BINARYWEIGHTEDDACFig. 3(a) shows a conceptual circuit of a 10-bit binary- weighted DAC. The digital inputs directly control the switches. The current sources associated with the switches are binary weighted. The advantage of such a binary-weighted DAC is its simplicity, as no decoding logic is required. There are several major drawbacks, however, which are all associated with major bit transitions. At the mid-code transition (01111111111000000000), the most significant bit (MSB) current source needs to be matched to the sum of all the othercurrent sources to within 0.5 LSB’s (least significant bits).This is difficult to achieve.。