芯片引脚功能说明.xls

Pin name VoltagePCI InterfacePCI_CLK 3.3PCI_RST 3.3PCI_AD[31:0] 3.3PCI_CBE[3:0] 3.3PCI_PAR 3.3PCI_IDSEL 3.3PCI_FRAME 3.3PCI_IRDY 3.3PCI_TRDY 3.3PCI_DEVSEL 3.3PCI_STOP 3.3PCI_GNT 3.3PCI_PERR 3.3PCI_SERR 3.3PCI_SERR 3.3PCI_INTA 3.3Gigabit Ethernet (SGMII/SERDES)GE[12:1]_RX+ 1.25GR[12:1]_RX- 1.25GE[12:1]_TX+ 1.25GE[12:1]_TX- 1.25GE_TEST[2:0] 1.25GE_CLK[2:0]+ 1.25GE_CLK[2:0]- 1.25MIIM InterfaceMIIM_MDC 3.3MIIM_MDIO 3.3JTAG InterfaceJTAG_TCK 3.3JTAG_TRST 3.3JTAG_TMS 3.3JTAG_TDI 3.3JTAG_TDO 3.3I2C InterfaceI2C_RESERVED 3.3I2C_SCL 3.3I2C_SDA 3.3I2C_SA[1:0] 3.3LED Controller InterfaceLED_CLK 3.3LED_DATA 3.3Test Signals 3.3TEST_GE0_RXD[9:0 3.3TEST_GE0_RXCLK 3.3TEST_GE0_TXD[9:0] 3.3TEST_GE0_TXCLK 3.3TEST_GE1_RXD[9:0] 3.3TEST_GE1_RXCLK 3.3TEST_GE1_TXD[9:0] 3.3TEST_GE1_TXCLK 3.3TEST_RXMUX_D[19:0] 3.3TEST_RXMUX_CLK[1:0] 3.3TEST_TXMUX_D[19:0] 3.3TEST_TXMUX_CLK 3.3TAP_ENABLE 3.3TAP 3.3MiscellaneousMOD_ID[4:0] 3.3NC NCRESERVED 3.3链路指示全双工模式指示全双工冲突指示100M速度指示1000M速度指示模拟电压晶体电压模拟电压晶体接地接地锁相环接地调整电路接地调整电压DescriptionPCI clock, frequency up to 66 MHzPCI and system resetAddress and dataBus command and byte enablesParityInitialization device selectCycle frameInitiator readyTarget readyDevice selectStopRequestGrantParity errorSystem errorInterruptGigabit Ethernet (SGMII/SERDES)Gigabit port receive data (positive) for ports 1 to 12. Each GEport has a pair of differential receive inputs.Gigabit port receive data (negative) for ports 1 to 12. Each GEport has a pair of differential receive inputs.Gigabit port transmit data (positive) for ports 1 to 12. Each GEport has a pair of differential transmit outputs.Gigabit port transmit data (negative) for ports 1 to 12. Each GEport has a pair of differential transmit outputs.Reserved for factory use, must be left as a no-connect (NC)Gigabit port SerDes reference clocks (positive), differential 25MHz.There are three differential 25 MHz clocks, all of which mustbe driven.No phase relationship is required between the threedifferentclocks, although normally each clock would come from a separateoutput from the same clock buffer.Gigabit port SerDes reference clocks (negative), differential25MHz. There are three differential 25 MHz clocks, all of whichmust be driven. No phase relationship is required between the threedifferentclocks, although normally each clock would come from a separateoutput from the same clock bufferSerial management clock, used to communicate to external PHYdevices under software controlSerial management data, used to communicate to external PHY devicesJTAG test clockJTAG test reset, must be pulled low during normal switch operationJTAG test mode selectJTAG test data inJTAG test data outThis pin has no user function, and must be pulled low or left as ano-connect (NC).I2C Clock12C DATAI2C address select, selects least significant two bits of deviceI2C address for slave mode operation (may be overridden insoftware)LED controller clockLED controller dataReserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Reserved for factory use, must be left as a no-connect (NC)Module ID. Each switch device in the system must have a uniquemodule ID. These pins determine the Module ID for the device uponreset and also sets the MY_MODID field in the CONFIG register.This value may be changed by software.No Connect, must be left as a no-connect signalReserved for factory use, must be connected to ground through apull-down resistor.链路指示全双工模式指示全双工冲突指示100M速度指示1000M速度指示模拟电压晶体电压模拟电压晶体接地接地锁相环接地调整电路接地调整电压PCI时钟PCI系统复位地址线数量线总线指令PCI奇偶选择初始程序选择周期设计主设备准备好重设备准备好程序选择停止请求同意PCI奇偶错误系统错误中断G Bit PORT 口界面时钟 正G Bit PORT 口界面时钟 负串行数据管理时钟串行数据管理输入输出G Bit接收信号 正负G Bit发送信号 正负I2C总线选择LED控制时钟LED控制数据错误指示链路指示链路 传输 指示链路 传输 速度指示带宽利用全双工模式指示全双工冲突指示100M速度指示1000M速度指示发送数据控制发送 接收信号25MHZ的晶体频率输入输出硬件复位输入信号发送时钟数据发送输出1G 链路指示10M.100M链路指示传输指示冲突指示数据管理或数据控制发送数据控制接收时钟数据接收数据接收控制串行程序主设备输出从设备输入数据输入输出管理串行程序从设备选择LED编程并口LED变换时钟串行LED数据输出串行程序启动时钟开启流量控制关闭流量控制系统时钟选择开启广播过滤串行程序主设备输入从设备输出开启全双工自动模式关闭全双工自动模式LED配置模式CPU或EEPROM界面选择EEPROM型号选择串行程序主设备输出从设备输入模拟电压控制调整输出电压TXC时钟延时RXC时钟延时DAC偏置电阻锁相环控制数字核心电压开启广播过滤启动PHY自动检测PHY地址顺序配置晶体电压模拟电压晶体接地接地锁相环接地调整电路接地调整电压偏置电压数字核心电压外围数字电压电压高速控制。