MIPI-DSI-Essential(MIPI协议详细介绍)演示课件.ppt

MIPI DSI EssentialTable of ContentsMIPI DSI OverviewPHY LayerD-PHY ArchitectureGlobal OperationLane Management LayerDSI Protocol Layer2MIPI DSI OverviewSerial Interface Low Pin Count Reduced Power Consumption 2 Types of Data Signaling High Speed Data Transmission - 500Mbps/Lane, differential signalingLow Power Data Transmission - 10Mbps, single ended signaling, lane 0 onlyLane-Scalable, up to 4 data lanesPacket Based Data TransmissionDSI Protocol has ECC, CRC capability - robust data transmission Protocol Support Multiple displays (up to 4)Support All Legacy Parallel Interface FunctionalityMIPI DSI Command Mode - MIPI DBI Interface (I-80 Interface)MIPI DSI Video Mode - MIPI DPI Interface (RGB Interface)3MIPI DSI Interface Physical Architecture 1 Clock Lane, unidirectional 1 to 4 Data Lanes Lane0 is bidirectional for LP data output transmission of the driver IC4MIPI DSI Functional LayersTransmitter Side8-bits8-bitsLow Level ProtocolDataControlDataControlAdd (TX) / Extract (RX) low level protocol, synchronization, ECC, CRC packet headers and footers.Low Level ProtocolDataControlDataControlN * 8-bitsTX: Distribute data to 1, 2, 3 or 4 lanesRX: Assembly data from 1, 2, 3 or 4 to one byte stream8-bits8-bitsLane Management LayerLane Management LayerReceiver SidePHY LayerData3ControlPHY LayerControlPixel to Byte Packing FormatsDataControlPixelControlPack / Unpack Pixels or Commands from / to Byte StreamByte to Pixel Unpacking FormatsDataControlPixelControlApplicationPixelControlApplicationPixelControlEncode and Interpretat Data / Commands16-, 18- or 24-bit PixelsData2 Data1 Data0N * 8-bitsData1 Data3 Data3Data0High Speed Unidirectional ClockLane 0 -High Speed bidirectional DataLane 1 -High Speed Unidirectional DataLane 2 -High Speed Unidirectional DataLane 3 -High Speed Unidirectional DataPhysical Transmission / ReceptionSerializer / DeserializerByte Clock Generation / Recovery (DDR) per MIPI D-PHY Spec5Video Mode DisplayDisplay DriverHostProcessorDisplay PanelLCD DisplayBusInterfaceBusInterfaceColor Frame BufferDisplay RefreshTimingControlUpdateFrameBuffer6Command Mode DisplayHostProcessorDisplay PanelLCD DisplayBusInterfaceColor Frame BufferImage UpdateDataCommands & Image UpdateDataBusInterfaceDisplay Controller7PHY LayerD-PHY ArchitecturePHY Lane ConfigurationMinimum ConfigurationAt least 1 Clock Lane, 1 Data LaneReverse-direction traffic uses lane 0 onlyLane 1, 2, 3 (if present)are unidirectionalLane number fixed at design / manufacture(Module level)No dynamic lane configuration by host processor.9D-PHY Lane Module (1/2)Transmission data Unit One byteLane Module may contain HS-TX, HS-RX, or bothIf LP mode is used at command mode configuration , both host and peripheral must include LP Rx and LP TxAlso CD needed if bi-directional in use The LP-CD shall check for contention at least once before driving a new state on the lineMaster and a Slave concept10D-PHY Lane Module (2/2)Low power transmitterHigh speed receiverLow power receiverContention (=“collision”) detectionHigh speed transmitter11Least PHY Lane Configuration - Detailed ViewData lane 0CLK lane* Bi-directional but not HS reverse* LP for bi-directional* uni-directional * LP for minimum transition control12D-PHY Signal Level2 Types of Signal LevelHSDTLPDTLP VOH - typ 1.2V, 1.1V 1.3VHS diff - typ 200mv, 140mv 270mvHS comm - typ 200mv, 150mv 250mvLP VOH - typ 0V, -50mV 50mVLP VIL : 550mVLP VIH -typ 1.2v 0.88V 1.35V13HS Mode- Transmitter Receiver StructureHS Data TransmissionWhile HSDT is active, Termination R is enabled R-term(ZID) : 100OhmTransmitter sideReceiver sidePCB, Conn, FPCB0V400mV300mV100mV14HS Mode - Signaling Detailed View 300mv100mv200mv100mv200mvVdiff = |VOD|Vdiff 200mV, Vcm 200mV Typ Condition15HS Mode - Clock Transmission HS Clock DDR Clock Structure, 1 Clk Period : 2*UIClock Burst always contains an even number of transition Clock can also run while D0 is in LP mode (especially Videomode)Ex) 500Mbps Freq : 250Mhz, 1Clk Period : 4ns, IU = 2ns, 16HS Mode - Clock to DataData to Clock Timing Definition90 Degree Phase Shift CLK to DataThe First bit of DSI Packet must be sent at a rising edge of HS ClkData LaneClock Lane17HSDT Signal in PracticeVCM = 200mV nomVo+ : typically 300mVVo- : typically 100mVVdiff(positive)18LP Signaling Detailed ViewTypically 1.2VTLPX - min : 50ns19LPDT Signal in Practice2TLPXtypically 1.2VDPDN20PHY LayerGlobal OperationData Unit Of D-PHYMinimum Data Unit is 1 ByteTransmitter - Byte stream - Bit streamReceiver - Bit stream - Byte streamHS Lane can be differential 1 or 0LP Lane on D0 can have four state(LP +/-)LP00 : Bridge, SpaceLP01 : HS-Rqst, Mark-0LP10 : LP-Rqst, Mart-1LP11 : Stop22D-PHY Operation Flow DiagramLP-11(Stop) State The start state of every operation.Major Three Type ModesEscape ModeHSTBus Turn AroundPHY State is decided by LP stateHSDT : LP11 - LP01 - LP00 - HSDT - LP-11LPDT : LP11 - LP10 - LP00 - Escape Mode - LP11In Case of Clock LaneHST is Supported for Clock Supply23Escape Mode OperationEscape Mode En。