静态时序分析总结资料.pdf

2013-3-191 Static Timing Analyzer Using PrimeTime Dec 23 2007 Presented by zhao icdesign_zhao@ 2 2013-3-19 Agenda ?Basic Flow ?Advanced Analysis ?Summary ?Example 3 2013-3-19 STA instruction ?Static timing analysis concept ? Verifies timing (setup, hold …) ? Is exhaustive ? Uses formal, mathematical techniques instead of vectors ? Does not use dynamic logic simulation ?STA : Easier, faster debugging of your design timing 4 2013-3-19 Comprehensive Timing Checks ? Many types of timing and design rule checks ? Timing checks can be delay calculated or SDF annotated ? Setup and hold check ? Design rule checks consistent with DC, PC, Astro 5 2013-3-19 Basic Timing Analysis Flow Using PrimeTime ?Setup Design Environment ?Search path, link path ?Read designs, libraries, then link ?Read sdf and set operation condition, environment setting ?Specify Timing Assertions ?Clock period/waveform/uncertainty/latency ?Input/output delays ?Specify Timing Exceptions ?Multi-cycle paths and False paths ?Min/max delays, segmentation, disabled arcs ?Perform Analysis, Create Reports ?Check timing ?Timing reports and constraint reports ?Bottleneck and coverage analysis reports 6 2013-3-19 Set Up Environment ?Definitions search_path:specifies where to search for design and library data link_path:specifies which design and library data to be loaded during linking (link_design) link_design:command resolves all design references ?Example: pt_shell set search_path “. ./syn/lib” pt_shell set link_path “* stdcell.db. IO.db memory.db” pt_shell read_verilog $project_dir/top.v pt_shell current_design top pt_shell link_design pt_shell read_sdf -type sdf_max $sdf_dir/top.sdf ?Design tip 1. The setup is different with DC setup 2. Before new design was load, removed old design and constraint 3. report_annotated_delay: Report backannotated delays 4. report_annotated_check: Report backannotated timing checks 7 2013-3-19 Operating condition and design environment ?Setting the operating conditions, wire-load models, input/output environment ?Example pt_shell set_operating_conditions -library pt_lib \ -analysis_type on_chip_variation worst pt_shell set_wire_load_mode enclose (pre gate) pt_shell set_wire_load_model std_100k_w (pre gate) pt_shell remove_wire_load_model (post gate) pt_shell set_driving_cell -lib_cell OR2 [all_inputs] (core level) pt_shell set_driving_cell -lib_cell IO/PAD (chip level) pt_shell set_load -load_of [expr std/nd2/A*8] (core level) pt_shell set_load -load_of [expr IO_CELL1/A*8] (chip level) ?Design tip 1. Wire load model is different in pre-gate and post-gate 2. Load and drive are different between core level and chip level 3. report_design: report operation conditions 8 2013-3-19 Clock assertions ?The basic timing assertions for the design always from Clock information ?Example pt_shell create_clock -name CLK -period 30 [get_port CLOCK] pt_shell set_clock_uncertainty -setup 0.5 [all_clocks] pt_shell set_clock_uncertainty -hold 0.5 [all_clocks] pt_shell set_clock_latency -min 3.5 [get_clocks CLK] pt_shell set_clock_latency -max 5.5 [get_clocks CLK] pt_shell set_clock_transition -rise 0.25 [get_clocks CLK] pt_shell set_clock_transition -fall 0.3 [get_clocks CLK] pt_shell set_propagated_clock [all_clocks] (post-gate) ?Design tip 1. Clock uncertainty is different between pre-gate and post-gate 2. Internal clock and external clock set different 3. Post-gate set to propagate clock 4. Created clock should be in port or cell pin 9 2013-3-19 Input and output delay assertions ?Specify signal arrival/required times at all ports relative to clocks in chip level ?Example pt_shell set_input_delay 5.0 -clock ClkA [all_inputs] pt_shell set_input_delay 3.0 -clock Vclk [remove_from_collection [all_inputs] [get_port clki]] pt_shell set_output_delay 4.0 -clock ClkB [get_ports input2] ?Design tip 1. For bidirectional ports, use both set_input_delay and set_output_delay 2. To asynchronous IO, using virtual clock to set delay 10 2013-3-19 Timing Exceptions (1) ?Timing exceptions (multi-cycle and false) Setup multi-cycle:The maximum number of clock cycles allowed for a signal to traverse a given path Hold multi-cycle:The number of clock cycles before the hold check False path: Ignored the special path timing check ?Example pt_shell set_multicycle_path -setup 2 -hold 1 -from rega/Q -to regb/D pt_shell set_multicycle_path -setup 4 -hold 3 -through A -through B pt_shell set_false_path -from clkA -to clkB pt_shell set_false_path -from rega/Q -to regb/D ?Design tip 1. False time setting can reduce CPU runtime 2. Timing exceptions must be cautious and reasonable 3. The set point should be pin or port for the compatible in gate and RTL 11 2013-3-19 Timing Exceptions (2) ?Timing exceptions (max/min delay, disable arcs) Max/min delay:Normally, the constraint was used in Asynchronous combinational logic that can’t be set by clock. Disable arcs:Ignore the path timing check through arc ?Example pt_shell set_max_p。