各种视频插头插座接口介绍.pdf

各种视频插头插座接口介绍(引脚定义) 各种视频插头插座接口介绍(引脚定义) SCART plug & connector: CENELEC (Comité Européen de Normalisation Electrotechnique) EN 50 049-1 / IEC 933-1 Pin No. Signal Inter Conne-ction Pin No. 1 Audio right channel output (0.5 Vrms, 10K ohms) 1 3 Audio left channel output (0.5 Vrms, 10K ohms) 3 7 Blue signal I/O (0.7 Vp-p, 75 ohms) 7 8 Function switching I/O (L: 10V, 10K ohms) 8 9 Green signal ground 9 10 Intercommunication data line No. 1 10 11 Green signal I/O (0.7 Vp-p, 75 ohms) 11 12 Intercommunication data line No. 2 12 13 Red signal ground 13 14 Blanking signal ground 14 15 Red signal I/O (0.7 Vp-p, 75 ohms) 15 16 Blanking signal I/O (L: 1.0V, 75 ohms) 16 17 Composite video signal ground 18 18 Blanking signal ground 17 19 Composite video signal output (1 Vp-p, 75 ohms, sync: negative) 20 20 Composite video signal input (1 Vp-p, 75 ohms, sync: negative) 19 21 Plug shield (common ground) 21 SCART 接口，是欧洲的标准视频接口， 传输 CVBS 信号、隔行 RGB 信号，通常厂家都把 SCART 用来传输 RGB 信号。

由于三原色信号分开传输，因此在色度方面表现比 S-Video 更好 SCART 现在只有传输 480I/576I 隔行信号的标准 EIAJ RGB plug & connector: EIAJ TTC-003 Outlook of plug and connector including pin assignment are the same as SCART plugand connector Pin No. Signal Inter Conne-ction Pin No. 1 Audio left channel input (0.40 mVrms, > 47K ohms) 1 2 Audio left channel output (0.40 mVrms, > 10K ohms) 2 3 Audio ground 3 4 Audio ground 4 5 Audio right channel input (0.40 mVrms, > 47K ohms) 6 6 Audio right channel output (0.40 mVrms, > 10K ohms) 5 7 Video ground 7 8 Video ground 8 9 CVBS input (1 Vp-p, 75 ohms, sync: negative) 10 10 CVBS output (1 Vp-p, 75 ohms, sync: negative) 9 11 AV control input 11 12 Ym input (switch for R, G & B signal to half tone level, L: 1.0, 75 ohms) 12 13 Red signal ground 13 14 Ground 14 15 Red signal I/O (0.7 Vp-p, 75 ohms) 15 16 Ys input (switch for R, G & B signal from/to internal and external, L: 1.0, 75 ohms) 16 17 Green signal ground 17 18 Blue signal ground 18 19 Green signal I/O (0.7 Vp-p, 75 ohms) 19 20 Blue signal I/O (0.7 Vp-p, 75 ohms) 20 21 Plug shield 21 Pin8 Switch – hystereticX = Not OK0V1V2V3V4V5V6V7V8V9V11V1,6V6,6VNOT OKNOT OKThe Function of SCART is recommended in EUROPEAN STANDARD EN 50049-1 The problem for Pin 8 detection is, that in specification is only descript the switch voltage levels on “transmitter” side. The TV-set is the “receiver”. 1. The TV-set should not change the display-mode (preset, format…) during Pin8 voltage in range of 0V to 2V. 2. The TV-set must switch to AV1 and format 16 : 9 during Pin8 voltage in range of 4,5V to 7,0V. 3. The TV-set must switch to AV1 and format 4 : 3 during Pin8 voltage in range of 9,5V to 12,0V. 4. In undefined (grey) ranges the state of TV-set is not specified.Therefore my proposal is, to eliminate the hysteretic in your Pin8-voltage detection and use a simple voltage detection like: 0V Upin8 100KW Chrominance (C) signal I/O (burst: 0.286 Vp-p, 75 ohms) Squeeze control input: + 5V DC / >100KW Letterbox control input: + 2.2V DC / >100KW EIAJ D-connector D1/2/3/4/5: EIAJ RC-5237 Pin No. Signal 1 Y signal I/O (+700 mV & sync: +/-300 mV *1, 75 ohms) 2 Y_GND 3 PB (+/- 350 mV, 75 ohms) 4 PB_GND 5 PR (+/- 350 mV, 75 ohms) 6 PR_GND 7 Reserved line 1 8 Line 1 (0V: 525 lines, 2.2V: 750 lines, 5V: 1125 lines) 9 Line 2 (0V: 59.94i / 60i, 2.2V: -, 5V: 59.94p / 60p) 10 Reserved line 2 11 Line 3 (0V: 4:3, 2.2V: 4:3 letter box, 5V: 16:9) 12 Plug insert detect GND 13 Reserved line 3 14 Plug insert detect (output: 10K ohms, input: >100K ohms) hooks Shell GND *1: for 1125i and 750p. -300mV for 525p/525i, superimposed in Y signal Note: Indication for video signal format (i: interlace, p: progressive) D1: 525i D2: 525i, 525p D3: 525i, 525p, 1125i D4: 525i, 525p, 1125i, 750p D5: 525i, 525p, 1125i, 750p, 1125p VESA DFP connector: VESA (Video Electronics Standards Association) Digital Flat Panel (DFP) Standard Pin No. Signal Name Signal 1 TX1+ TMDS positive differential output, channel 1 2 TX1- TMDS negative differential output, channel 1 3 SHLD1 Shield for TMDS channel 1 4 SHLDC Shield for TMDS clock 5 TXC+ TMDS positive differential output, reference clock 6 TXC- TMDS negative differential output, reference clock 7 GND Logic Ground 8 +5V Logic +5V DC Supply from the Host 9 No Connect No Connection 10 No Connect No Connection 11 TX2+ TMDS positive differential output, channel 2 12 TX2- TMDS negative differential output, channel 2 13 SHLD2 Shield for TMDS channel 2 14 SHLD0 Shield for TMDS channel 0 15 TX0+ TMDS positive differential output, channel 0 16 TX0- TMDS negative differential output, channel 0 17 No Connect No Connection 18 HPD Hot Plug Detection (+5V DC to Host) 19 DDC_DAT DDC2B Data 20 DDC_CLK DDC2B Clock TMDSTM: Transition Minimized Differential Signaling DDC: Display Data Channel DDC2B: Simplest of the DDC modes defined in the VESA DDC standard VESA P&D connector: Plug and Display Standard (P&DTM) Pin No.。