杭电计组实验-实现R型指令的CPU设计实验.docx

杭电计组实验-实现R型指令的CPU设计实验作者:日期:#实验报告姓名阳光男学号16041321班级16052317专业计算机科学与技术课程名称《计算机组成原理与系统结构试 验》任课老师张翔老师指导老师张翔老师机位号无实验序号8实验名 称《实验八 实现R型指令的CPU设计实验》实验时间2018/5/25实验地占八、、1 教 225实验设备 号个人电脑一、实验程序源代码顶层LED测试模块：module Top_LED(clk,rst,SW,LED);in put clk,rst;in put [2:0]SW;output reg[7:0]LED;wire ZF,OF;wire [31:0]ALU_F;top_R_cpu test_cpu(rst,clk,ZF,OF,ALU_F); always@(*)begi ncase(SW)3'b000:L ED=ALU_F[7:0];3'b001:LED=ALU_F[15:8];3'b010:LED=ALU_F[23:16];3'b011:LED=ALU_F[31:24];3'b100:begin LED[7:2]=0;LED[1]=0F;LED[0]=ZF;e nd default:LED=0;endcaseend2018年_6_月 1 日成绩： en dmodule顶层R型CPU模块：module top_R_cpu(input rst,input clk,output ZF,output OF,output [31:0]F); reg write_reg;wire [31:0]l nst_code;wire [31:0]R_Data_A;wire [31:0]R_Data_B;reg [2:0]ALU_OP;pc pc_c onn ect(clk,rst,I nst_code);Register_file R_co nn ect(I nst_code[25:21],l nst_code[20:16],In st_code[15:11],write_reg,F,~clk,rst, R_Data_A,R_Data_B);ALU ALU_co nn ect(R_Data_A,R_Data_B,F,ALU_OPOF);always@(*)begi nwrite_reg=0;ALU_OP=0;if(I nst_code[31:26]==0)begi ncase(I nst_code[5:0])6'b100000:ALU_OP=3'b100;6'b100010:ALU_OP=3'b101;6'b100100:ALU_OP=3'b000;6'b100101:ALU_OP=3'b001;6'b100110:ALU_OP=3'b010;6'b100111:ALU_OP=3'b011;6'b101011:ALU_OP=3'b110;6'b000100:ALU_OP=3'b111;endcasewrite_reg=1;endenden dmodulePC取指令模块：module pc(i nput clk,i nput rst,output [31:0]l nst_code); reg [31:0]PC;wire[31:0]PC_ new;in itialPC<=32'h00000000;In st_ROM In st_ROM1 (.clka(clk),.addra(PC[7:2]),.douta(I nst_code));assign PC_n ew二{24'h000000,PC_ new[7:0]}; always@ (n egedge clk or posedge rst) begi nif(rst)PC=32'h00000000;else PC=PC_new;enden dmodule寄存器堆模块:moduleB);Register_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data in put [4:0]R_Addr_A;in put [4:0]R_Addr_B;in put [4:0]W_Addr;in put Write_Reg;in put [31:0]W_Data;in put Clk;in put Reset;output [31:0]R_Data_A;output [31:0]R_Data_B;reg [31:0]REG_Files[0:31];#initial//仿真过程中的初始化begi nfor(i=0;iv=31;i二i+1)REG_Files[i]=O;endassign R_Data_A=REG_Files[R_Addr_A]; assign R_Data_B=REG_Files[R_Addr_B]; always@(posedge Clk or posedge Reset) begi nif(Reset)for(i=0;i<=31;i=i+1)REG_Files[i]=O;elseif(Write_Reg&&W_Addr!=0)REG_Files[W_Addr]=W_Data;enden dmoduleALU算术逻辑运算单元模块：module ALU(A,B,F,ALU_QZF,OF);in put [31:0]A,B;in put [2:0]ALU_OP;output reg ZF,OF;output reg[31:0]F;reg C32;always@(*)begi nOF=1'b0;C32=1'b0;case(ALU_OP)3'b000:F=A&B;3'b001:F=A|B;3'b010:F=AAB;3'bO11:F=~(A^B);3'b100:begin {C32,F}=A+B;OF=A[31]AB[31]AF[31]AC32;e nd3'b101:begin {C32,F}二A-B;OF二A[31]AB[31]AF[31FC32;e nd 3'b110:if(A