Quartus常见错误分析 Error.docx

Quartus常见错误分析 Error Quartus常见错误分析Error Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list ----没把singal放到process〔〕中 2 Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock -=-----可能是说设计中产生的触发器没有使能端 3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object \of mode out cannot be read. Change object mode to buffer or inout. ------信号类型设置不对，out当作buffer来定义 4 Error: Node instance \instantiates undefined entity \ -------引用的例化元件未定义实体－－entity \ 5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock \as buffer Info: Detected ripple clock \as buffer 6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable %ut\may not be assigned a new in every possible path through the Process Statement. Signal or variable \dataout\holds its previous in every path with no new assignment, which may create a combinational loop in the current design. 7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal \is read inside the Process Statement but isn't in the Process Statement's sensivitity list -----缺少敏感信号 8 Warning: No clock transition on \register 9 Warning: Reduced register \with stuck clock port to stuck GND 10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \with clock skew larger than data delay. See Compilation Report for details. 11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \with clock skew larger than data delay. See Compilation Report for details. 12 Error: VHDL error at counter_clk.vhd(90): actual port \class\of mode \cannot be associated with formal port \of mode \ ------两者不能连接起来 13 Warning: Ignored node in vector source file. Can't find corresponding node name \s_sig[2]\in design. ------没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射 14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port \ in design entity does not have std_logic_vector type that is specified for the same generic in the associated component ---在相关的元件里没有当前文件所定义的类型 15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal \because signal does not hold its outside clock edge 16 Warning: Found clock high time violation at 1010.0 ns on register \ 17 Warning: Compiler packed, optimized or synthesized away node \Ignored vector source file node. ---\被优化掉了 18 Warning: Reduced register \with stuck data_in port to stuck GND 19 Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin \ Warning: No output dependent on input pin \ ------输出信号与输入信号无关， 20 Warning: Found clock high time violation at 16625.0 ns on register \ 21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator \ 22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter \but formal parameter is not declared -------连接表错误，形参\赋值给实参，形参没定义，可能是形参加实参的位置颠倒了，规定形参在实参之前。

23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors －－－－－－－－因为前一个错误而导致的错误 24 Error: VHDL error at period_counter.vhd(38): type of identifier \does not agree with its usage as std_logic type －－－－－－－－\的定义类型与运用的类型不相同 25 Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks -------同一进程中含有两个或多个if(edge)条件，〔一个进程中之能有一个时钟沿〕 26 Error: Can't resolve multiple constant drivers for net \at shift_reg.vhd(19) 27 can't infer register for signal \because signal does not hold its outside clock edge 28Error: Can't elaborate top-level user hierarchy 29 Error: Can't resolve multiple constant drivers for net \at led_key.vhd(32) ----------有两 个以上赋值语句，不能确定“cs_in”的值， 30 Warning: Ignored node in vector source file. Can't find corresponding node name \\in design. ---------------在源文件中找不到对应的节点“over”。

31 Error: Can't access JTAG chain 无法找到下载链 32 Info: Assuming node \is an undefined clock Quartus警告分析Warning 1.Found clock-sensitive change during active clock edge at time on register \ 缘由：vector source file中时钟敏感信号〔如：数据，允许端，清零，同步加 载等〕在时钟的边缘同时改变而时钟敏感信号是不能在时钟边沿改变的其后 果为导致结果不正确 措施：编辑vector source file 2.Verilog HDL assignment warning at : truncated with size to match size of target ( 缘由:在HDL设计中对目标的位数进展了设定,如:reg[4:0] a;而默认为3。