
用verilog编写fpga的vga显示
10页1、用verilog编写fpga的vga显示()VGA工业标准是640x480x60Hz,主要有5个信号,即三个颜色信号R/G/B、行同步信号HS和场同步信号VS。它是从左上角开始一行接一行的扫描,扫描完一屏后又回到左上角扫描。标准要求是场频59.94Hz,行频31469Hz,时钟频率25.175MHz这是Altera的DE2开发板上自带的演示程序。可以先搜一下VGA工业标准的时序图,再看这个代码就会很简单,就不注释了。弄清楚行同步、场同步、前肩、后肩,一切都easymodule VGA_Controller( / Host Side iRed, iGreen, iBlue, oRequest, / VGA Side oVGA_R, oVGA_G, oVGA_B, oVGA_H_SYNC, oVGA_V_SYNC, oVGA_SYNC, oVGA_BLANK, oVGA_CLOCK, / Control Signal iCLK, iRST_N );include VGA_Param.h/ Host Sideinput 9:0 iRed;input 9:0 iGreen;input 9:0
2、iBlue;output reg oRequest;/ VGA Sideoutput 9:0 oVGA_R;output 9:0 oVGA_G;output 9:0 oVGA_B;output reg oVGA_H_SYNC;output reg oVGA_V_SYNC;output oVGA_SYNC;output oVGA_BLANK;output oVGA_CLOCK;/ Control Signalinput iCLK;input iRST_N;/ Internal Registers and Wiresreg 9:0 H_Cont;reg 9:0 V_Cont;reg 9:0 Cur_Color_R;reg 9:0 Cur_Color_G;reg 9:0 Cur_Color_B;wire mCursor_EN;wire mRed_EN;wire mGreen_EN;wire mBlue_EN;assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC;assign oVGA_SYNC = 1b0;assign oVGA_CLOCK = iCLK
3、;assign oVGA_R = ( H_Cont=X_START & H_Cont=Y_START & V_Cont=X_START & H_Cont=Y_START & V_Cont=X_START & H_Cont=Y_START & V_ContY_START+V_SYNC_ACT ) ? iBlue : 0;/ Pixel LUT Address Generatoralways(posedge iCLK or negedge iRST_N)begin if(!iRST_N) oRequest =X_START-2 & H_Cont=Y_START & V_ContY_START+V_SYNC_ACT ) oRequest = 1; else oRequest = 0; endend/ H_Sync Generator, Ref. 25.175 MHz Clockalways(posedge iCLK or negedge iRST_N)begin if(!iRST_N) begin H_Cont = 0; oVGA_H_SYNC = 0; end else begin / H
4、_Sync Counter if( H_Cont H_SYNC_TOTAL ) H_Cont = H_Cont+1; else H_Cont = 0; / H_Sync Generator if( H_Cont H_SYNC_CYC ) oVGA_H_SYNC = 0; else oVGA_H_SYNC = 1; endend/ V_Sync Generator, Ref. H_Syncalways(posedge iCLK or negedge iRST_N)begin if(!iRST_N) begin V_Cont = 0; oVGA_V_SYNC = 0; end else begin / When H_Sync Re-start if(H_Cont=0) begin / V_Sync Counter if( V_Cont V_SYNC_TOTAL ) V_Cont = V_Cont+1; else V_Cont = 0; / V_Sync Generator if( V_Cont V_SYNC_CYC ) oVGA_V_SYNC = 0; else oVGA_V_SYNC =
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