基于veriloghdl语言的串口设计.doc

基于Verilog HDL语言的串口设计串 UVerilog HDL 代码://串口module trans(clk,rst,en,TxD_data,Wsec,RxD,TxD,TxD_busy,rcven,RxD_data);// 时钟 50MHzinput clk,rst,en; //en吋发送数据使能 input [7:0]TxD_data;//发送数据输入input [2:0]Wsec;//波特率调节 0-2400; 1-4800； 2-9600； 3-14400； 4-19200； 5-38400； 6-115200； 7-128000input RxD; //接收数据输入端output TxD、TxD_busy,rcven;//发送，发送把，接收结束标志输出 output [7:0]RxD_data;//接收数掘输出wire Baudl,Baud8;reg [7:0]addwire;//RAM 地址连线reg [7:0]data;wire[7:0]AD_t;//读取RAM数据的地址用于发送 wirep:0]AD_r;//接收的数据存储在RAM中的地址 wire [7:0]datawire;//数据连线//发送例化trans一t ttl(.clk一t(clk)"rst_t(rst)"en_t(en)"BTI_t(Baudl),.recen(recen),.TxD_data_t(datawire)/.TxD_t(TxD),.addro_t(AD_t)/TxD_busy_t(TxD_busy));//波寺生A例化BaudG tt2(.clk_b(clk),.rst_b(rst),.BTO_b(Baudl),.BTO_R(Baud8),.Wsec_b(Wsec));//接收例化trans_r tt3(.clk_r(clk)/.rst_r(rst),.BTI_r(Baud8),.RxD_r(RxD)/.RxD_data_r(RxD_data)z.wren_r(wren_r)/.addro_r(AD_r),.RxD_end(RxD_end));"LPM一RAM 例正RAM0tt4(.address(addwire)"clock(〜clk)"data(data),.wren(wren_r),.q(datawire)); always @(posedge elk or negedge rst)if(~rst)addwire <= 8bOOOOOOOO; else if(RxD_end)beginaddwire <=AD_r ;data<=RxD_data; endelse addwire<=AD_t;endmodule//发送模块moduletrans_t(clk_t,rst_t,en_t,BTI_t,TxD_data_t,TxD_t,recen,TxD_busy_t,addro_t,recen );input clk_t,rst_t,en_t,BTI_t; input [7:0]TxD_data_t; output TxD_t; output TxD_busy_t; output recen; output [7:0]addro_t;reg TxD_t;reg [7:0]TxD_dataReg;//寄存器reg [7:0]addro_t；//reg [3:0]state;reg recen;wire TxD_busy_t;assign BaudTick = BTI_t;//波特输出//发送启动wire TxD_ready = (state==0); // TxD_ready = 1 assign TxD_busy_t =〜TxD一ready;//加载发送数i "always @(posedge clk_t or negedge rst_t) if(〜rst_t)TxD_dataReg <= 8bOOOOOOOO; else if(TxD一ready && en_t)TxD_dataReg <= TxD_data_t;//状态机发送always @(posedge clk_t or negedge rst_t) if(〜rst」)beginstate <= 4bOOOO; // 复位时发送 1 TxD_t <= lbl;endelsecase(state)4b0000: if(en_t ) beginstate <= 4bOlOO; //检测发送开始 end4bOlOO: if(BaudTick && en_t) beginstate <= 4blOOO; // 发送起始位 0TxD_t <= 1bO;end4blOOO: if(BaudTick && en—t) beginstate <= 4blOOl; // bit 0if(en_t) TxD_t <= TxD_dataReg[O]; else TxD」<=l*bO;end4blOOl: if(BaudTick && en—t) beginstate <= 4blOlO; // bit 1if(en_t) TxD_t <= TxD_dataReg[l]; else TxD」<=l*bO;end4blOlO: if(BaudTick && en_t) beginstate <= 4blOll; // bit 2if(en_t) TxD_t <= TxD_dataReg[2]; else TxD」<=l*bO;end4blOll: if(BaudTick && en_t) beginstate <= 4bllOO; // bit 3if(en_t) TxD_t <= TxD_dataReg[3]; else TxD」<=l*bO;end4bllOO: if(BaudTick && en_t) beginstate <= 4bllOl; // bit 4if(en_t) TxD_t <= TxD_dataReg[4]; else TxD」<=l*bO;end4bllOl: if(BaudTick && en_t) beginstate <= 4blllO; // bit 5if(en_t) TxD_t <= TxD_dataReg[5]; else TxD」<=l*bO;end4blllO: if(BaudTick && en_t) beginstate <= 4bllll; // bit 6if(en_t) TxD_t <= TxD_dataReg[6]; else TxD」<=l*bO;end4bllll: if(BaudTick && en_t) beginstate <= 4bOOlO; // bit 7if(en_t) TxD_t <= TxD_dataReg[7]; else TxD」<=l*bO;end4bOOlO: if(BaudTick && en—t) beginstate <= 4b0011; // stoplTxD_t <= lbl;end4bOOll: if(BaudTick) beginstate <= 4bOOOO; // stop2 TxD t <= lbl;enddefault: if(BaudTick) beginstate <= 4bOOOO;TxD一t <= lbl;endendcasealways @(posedge clk_t or negedge rst_t) if(~rst_t)begin recen<=O;end else if(〜TxD_ready)recen<=l;else recen<=0;//地址计数器ddressalways @(posedge clk_t or negedge rst_t) if(〜rst_t)addro_t <= 8bOOOOOOOO; else if(TxD_ready && enj)addro t <=addro t +1;endmodule//波特生成模块module BaudG(clk_b,rst_b,BTO_b,BTO_R,Wsec_b);input clk_b,rst_b; input [2:0]Wsec_b; output BTO_b,BTO_R;reg FT,FT8;reg [16:0]BGA;reg [16:O]BGA1;wire BTO_b = FT; //发送波特wire BTO_R = FT8;//接收模块波特=发送*16always @(posedge clk_b or negedge rst_b ) if(〜rst一b)begin BGA <= O;BGA1 <= 0;endelsecase(Wsec_b)0:beginif(BGAl>1302)begin FT8=lbl; BGAl<=0; end//接收波特=2400*16else begin FT8=lbO; BGA1 <= BGA1+ 1;endif(BGA>62500)begin FT=l,bl;FT8=l,bl; BGAl<=0; BGA<=0; end // 发送波特=2400else begin FT=lbO; BGA <= BGA+ 3; endend1: begin if(BGAl>651)begin FT8=l*bl; BGAl<=0; end // 接收波特=4800*16else begin FT8=lbO; BGA1 <= BGA1+ 1;endif(BGA>62500)begin FT=lbl; FT8=lbl; BGAl<=0;BGA<=0; end // 发送波特=4800else begin FT=lbO; BGA <= BGA+ 6; endend2: begin if(BGAl>651)begin FT8=lbl; BGAl<=0; end // 接收波特=9600*16else begin FT8=lbO; BGA1<= BGA1+ 2; end if(BGA>15625)begin FT=lbl;FT8=l,bl; BGAl<=0;BGA<=0; end // 发送波特=9600else begin FT=lbO; BGA <= BGA+ 3; endend3: begin if(BGAl>217)begin FT8=lbl; BGAl<=0; end // 接收波特=14400* 16else begin FT8=lbO; BGA1 <= BGA1+ l;end if(BGA>17361)begin FT=l,bl;FT8=l,bl; BGAl<=0;BGA<=0; end // 发送波特=14400else begin FT=lbO; BGA <= BGA+ 5; endend4: begin if(BGAl>651)begin FT8=lbl; BGAl<=0; end // 接收波特=19200*16else begin FT8=lbO; BGA1 <= BGA1+ 4;end if(BGA>15625)begin FT=lbl; FT8=lbl;BGAl<=0;BGA<=0; end // 发送波特=19200else begin FT=l,bO; BGA <= 。