ghz级数字模块的测试结构设计与实现.pdf

国防科学技术大学 硕士学位论文 GHz 级数字模块的测试结构设计与实现 姓名：章胜 申请学位级别：硕士 专业：软件工程 指导教师：马驰远 2011-04 国防科学技术大学研究生院工程硕士学位论文 第 i 页 摘 要 随着集成电路设计技术的飞速发展和集成电路工艺特征尺寸的不断缩小，各 种微观效应的影响愈加突出，这将导致电路在流片后实测结果与流片前分析结论 的一致性逐渐变差因此，为确保芯片设计的正确性，电路需要进行流片测试 本文针对 GHz 级数字模块的测试结构展开研究，GHz 级数字模块具有较多的高速 输入输出端口， 直接引出测试需要使用众多价格昂贵的高速 I/O， 这将导致高速 I/O 电路占用了很大的芯片面积，且封装和测试成本很高因此，本文的目标是研究 和设计一种引脚少、成本低且支持 GHz 级时钟可变频调测试的可重用数字关键模 块流片后测试结构 本文针对 GHz 级数字关键模块电路的流片后测试难点， 提出了一种 GHz 级数 字模块流片后测试的设计方案， 并实现了一款 65nm CMOS 工艺下全定制 CAM 模 块的流片后测试设计文章的主要工作和创新点如下： 1. 采用 JTAG 协议和扫描链设计技术相结合的策略，在不降低待测数字模块 内部输入输出端口的可控制性和可观察性的前提下，有效减少了输入输出引脚的 数目。

2. 提出一种时钟可变频和时钟频域切换的设计方法，有效解决了流片后性能 测试频点需求多和功能测试高频输出响应成本开销大的难题本文性能测试频点 的可配置范围为 10MHz-2.4GHz，可以完全满足流片后高频率和多频点的测试需 求 3. 基于 65nm CMOS 工艺，采用半定制流程实现了 GHz 级数字模块流片后测 试结构，并完成了一款全定制 CAM 的流片测试实现版图实现面积为 0.385mm， 与同类的测试方案相比，本设计的面积节约较多此外，本设计采用低频率时钟 输出响应，不需要高速 I/O，使得测试成本大大降低 关键词：JTAG；功能测试；性能测试；时钟切换；扫描链技术 国防科学技术大学研究生院工程硕士学位论文 第 ii 页 ABSTRACT With the rapid development of integrated circuits design and technology scaling, many parasitic effects become more severe, which lead to unconsistency between the test results of real chip and the analysis before taping out. Therefore, circuits must be verified through taping-out in order to ensure the correctness of chip design. This thesis investigates the test architecture of digital module in GHz level. GHz level digital module has a lot of input-output ports. The common used direct test method needs many expensive and high speed I/O pins which will occupy a majority of chip area and the packaging cost of high frequency chip is very high. So this thesis tries to design a reusable taping-out test architecture with little pins and low cost which can also surport the debug and test of clock frequency ranging in GHz level. A solution of GHz level digital module taping-out test against the problems metioned above is presented in this thesis, and a full-custom CAM taping-out test in 65nm CMOS process is also implemented. The main contribution and innovative points are as follows: 1. The strategy of combining the JTAG protocol and scan chain technology is applied. The strategy can not only reduce the number of pins effectively, but also realize the fully controllability and observability. 2. The design method of clock alterable frequency and clock frequency switching is proposed, which can solve the problem of requiring multi-frequency points in taping-out performance test structure and high cost in functional testing. The range of reconfigurable performance points of test frequency is between 10MHz and 2.4GHz which can meet the demands of performance test. 3. Based on 65nm CMOS process and using semi-custom design flow, a GHz level digital module taping-out test architecture has been implemented. The taping-out test implementation of a full-custom design of CAM has been completed. Its layout area is 0.385 mm2. In contrast with the similar method, this design saves much more area. Besides, it doesn’t use high speed I/O interfaces to output response which can reduce cost greatly. Key Words:JTAG, Function Testing, Performance Testing, Clock Frequency Switching, Scan Chain Technology 国防科学技术大学研究生院工程硕士学位论文 第 IV 页 表表 目目 录录 表 2.1 IRTS 技术指导: SIA Roadmap.......................................................................... 7 表 3.1 JTAG 方案和类似方案的比较 ....................................................................... 20 表 4.1 各个控制状态下指令寄存器的操作.............................................................. 33 表 5.1 PLL 操作状态.................................................................................................. 46 国防科学技术大学研究生院工程硕士学位论文 第 V 页 图图 目目 录录 图 2.1 测试原理图........................................................................................................ 8 图 2.2 测试成本的趋势图............................................................................................ 9 图 2.3 全扫描设计示意图.......................................................................................... 11 图 2.4 边界扫描测试结构示意图.............................................................................. 12 图 2.5 BIST 结构示意图 ............................................................................................ 13 图 3.1 定制 CAM 芯片的版图................................................................................... 17 图 3.2 数字模块测试结构总体框架图...................................................................... 19 图 3.3 测试逻辑的具体架构图.................................................................................. 22 图 3.4 测试逻辑的设计流程图.................................................................................. 23 图 4.1 边界扫描单元的测试示意图.......................................................................... 26 图 4.2 标准 JTAG 的内部结构 .................................................................................. 28 图 4.3 数字模块的 JTAG 逻辑结构 .......................................................................... 29 图 4.4 TAP 控制器的状态图.............................................................................。