verilogFPGA状态机描述.ppt

3-1Example: Example: 一段式状态机一段式状态机描述方法描述方法 stop: begin if ( A ) begin state <= clear; K2 <= 1; end else state <= stop; end clear: begin if ( !A) begin state <= idle ; {K2,K1} <= 2’b01; end else state <= clear ; end endcase endmodule module Mealy_state_machine (clock, reset, A, K2, K1 ); input clock, reset, A; output K2, K1; reg K2, K1; reg [1,0] state; parameter idle =2’b00, start =2’b01; stop =2’b10, clear =2’11; always @(posedge clock or negedge reset) if (!reset) begin state <= idle; {K2,K1} <= 2’b00; end else case (state) idle: begin if ( A) begin state <= start ; K1 <= 0; end else state <= idle ; end　　　start: begin if ( !A) state <= stop ; else state <= start ; end 3.5 状态机描述方法状态机描述方法3-2module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w; output oe,we; reg oe,we; reg [3,0] present_state, next_state; parameter idle =4’b0001, decision=4’b0010; read=4’b0100, write=4’1000; // sequential state transition always @ (posedge clock or negedge reset ) if ( !reset ) present_state <= idle ; else present_state <= next_state ; //combinational block always @(reset or present_state or rdy or r_w) begin case (present_state) idle: begin {oe,we} = 2’b00; if ( rdy) next_state = decision ; else next_state = idle ; end　　　decision: begin {oe,we} = 2’b00; if ( r_w) next_state = read ; else next_state = write ; end read: begin {oe,we} = 2’b10; if ( rdy) next_state = idle ; else next_state = read; end write: begin {oe,we} = 2’b01; if ( rdy) next_state = idle ; else next_state = write ; end default: begin {oe,we} = 2’b00; next_state = 4’bx ; end endcase end // end always begin endmodule;rdyrdyrdyr_wr_wResetrdyrdyidle00decision00write01read10StateidledecisionwritereadOutputsoe0001we0010Example: Example: 两段式状态机两段式状态机描述方法（推荐）描述方法（推荐）3-3module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w; output oe,we; reg oe,we; reg [3,0] present_state, next_state; parameter idle =4’b0001, decision=4’b0010; read=4’b0100, write=4’1000; // sequential state transition always @ (posedge clock or negedge reset ) if ( ! reset ) present_state <= idle ; else present_state <= next_state ; //combinational block always @(reset or present_state or rdy or r_w) begin case(present_state) idle: begin idle_output; if ( rdy) next_state = decision ; else next_state = idle ; end　　　decision: begin decision_output; if ( r_w) next_state = read ; else next_state = write ; end 　　　 read: begin read_output; if ( rdy) next_state = idle ; else next_state = read; end write: begin write_output; if ( rdy) next_state = idle ; else next_state = write ; end default: begin idle_output; next_state = 4’bx ; end endcase end //end always begin//output taskstask idle_output; {oe,we} = 2’b00;endtasktask decision_output; {oe,we} = 2’b00;endtasktask read_output; {oe,we} = 2’b10;endtasktask write_output; {oe,we} = 2’b01;endtaskendmodule;Example: Example: 两段式状态机描述使用两段式状态机描述使用tasktask（推荐编码）（推荐编码）3-4module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w; output oe,we; reg oe,we; reg [3,0] present_state, next_state; parameter idle =4’b0001, decision=4’b0010; read=4’b0100, write=4’1000; // sequential state transition always @ (posedge clock or negedge reset ) if ( ! reset ) present_state <= idle ; else present_state <= next_state ; //combinational block always @(reset or present_state or rdy or r_w) begin case (present_state) idle: begin if ( rdy) next_state = decision ; else next_state = idle ; end　　　decision: begin if ( r_w) next_state = read ; else next_state = write ; end 　　　 read: begin if ( rdy) next_state = idle ; else next_state = read; end write: begin if ( rdy) next_state = idle ; else next_state = write ; end default: begin next_state = 4’bx ; end endcase end //end always begin//Registered outputalways @ (posedge clock or negedge reset ) if ( ! reset ) {oe,we} <= 2’b00 else begin case(next_state) idle: {oe,we} <= 2’b00 ; decision: {oe,we} <= 2’b00; read: {oe,we} <= 2’b10; write: {oe,we} <= 2’b01; endcase endendmodule;Example: Example: 三段式状态机描述（推荐编码）三段式状态机描述（推荐编码）。