LDO滤开关噪声.docx

Minimizing switching regulator residue in linear regulator outputs-- Bani shi ng those accursed spikesIntroductionDC/DC + LDO :提高稳定性、精度、瞬态响应，降低输出阻抗理论上，还会显著降低纹 波和电压尖峰但实际上，LDO很难抑制开关稳压器产生的电压纹波、电压尖峰，开关频 率比较高时更难抑制，当Vin与Vout电压差较低时，这种影响会被进一步放大但是从效 率角度看，却希望Vin -VDUt的电压差越低越好输入滤波电容是为了平滑纹波和电压尖峰输出电容是为了维持较低的输出阻抗，提高负载 瞬态响应，对某些稳压器来讲，还有频率补偿的作用；附带的功能还包括降低噪声，最小化 由输入引起的输出电压波动理解噪声源头和本质是遏制的关键Figure 2. Switching Regulator Output Contains Relitively Low Frequency Ripple and High Frequency "Spikes" Derived From Regulators Pulsed Energy Delivery and Fast Transition Times这些高频噪声，即使幅值很小，也会对视频、通信和其他一些对噪声敏感的电路产生影响。

大量的电容和其他电路被用来消除这些不希望的信号及其影响Figure 1. Conceptual Linear Regulator and Its Filter Capacitors Theoretically Reject Switching Regulator Ripple and SpikesSwitching regulator AC output content开关电源的输出交流分量包含100kHz〜3MHz的开关频率纹波，及大约在100MHz的开关电 压尖峰（因为开关管的瞬态开关而产生的）参考上图LDO稳压电路滤波电容用来滤除这些电压尖峰，但是实际上不能全部消除降低开关稳压器的开关频率和 开关切换速度可以大大降低这些纹波及电压尖峰的幅值，但会导致磁性元件的尺寸增大，效 率降低Ripple and spike rejection线性稳压器对于开关频率纹波电压有较好的抑制作用，但是对非常宽频的尖峰抑制较差下图是LDO，LT1763，对不同频率的纹波的抑制性能100kHz时为40dB的纹波抑制比, 但是到1MHz的时候就跌落到了 25dBE-p 二Bi=Hr■臣LLJIdd 正40302010010100 1k 10k 100k 1MFREQUENCY (Hz)酿101 RBFigure 3. Ripple Rejection Characteristics far an LT1763 Low Dropout Linear Regulator Show 40dB Attenuation at 100kHz, Rolling Off Towards 1MHz. Switching Spike Harmonic Content Approaches 100MHz; Passes Directly From Input to Output本希望用输出滤波电容来吸收这些高频分量，但是其也有自身的高频性能限制。

下图为主要 考虑了高频寄生参数后的LDO稳压电路其中磁珠寄生电容、滤波电容的ESL和ESR、LDO 内部开关的寄生电容、电路板走线的寄生电容，组成了一个高通电路而且通过寄生电容会 影响LDO的reference及内部的放大器LAYOUT PARASITIC CIFF;AINPUT DC + RIPPLEAND SPIKES FROMSWITCHING REGULATORPARASITIC C厂T —n_* *-FERRITE BEAD」一FILTER OR INDUCTOR CAPACITORPARASITICLANDRPARASITICREGULATOR (FINITE GAIN-BANDWIDTHAND PSRR VS FREQUENCY)PARASITIC CFERRITE BEAD OR INDUCTOROUTPUTFILTER—T- CAPACITORPARASITICLANDRMONITORINGOSCILLOSCOPE* = GROUND POTENTIAL DIFFERENCES PROMOTE OUTPUT HIGH FREQUENCY CONTENT AND CORRUPT MEASUREMENT.Figure 4. Conceptual Linear Regulator Showing High Frequency Rejection Parasitics. Finite GBW and PSRR vs Frequency Limit Regulator's High Frequency Rejection. Passive Components Attenuate Ripple and Spikes, But Parasitics Degrade Effectiveness. Layout Capacitance and Ground Potential Differences Add Errors, Complicate Measurement识别这些高频参数很重要，对于测量和降低输出的高频分量都有帮助。

LDO的高频馈送路径，主要是影响reference的电容及影响内部放大器的电容它们与运放 有限的增益带宽一起限制了高频抑制能力输入输出滤波电容，由于寄生电感和电阻的存在，其滤波效果随着频率的升高而降低电路布局的杂散电容提供了不希望有的馈送路径地电平的差异（由走线电阻及电感引起的）增加了额外的输出误差，并且使测量更复杂其他因素：铁氧体磁珠、电感有各自的高频寄生回路，但是有很大的高频抑制作用Ripple/Spike Simulator为了很好地理解这个问题，需要观察LDO在不同工作状态下对纹波和电压尖峰的响应纹波、电压尖峰的参数包括：频率、谐波分量、幅值、持续时间，及直流电压值采用下图可模拟开关稳压器的输出，DC电压、纹波、电压尖峰参数均可调SVLT146O2.5VSPIKE WIDTHAMPLITUDE OUTPUTSYNC.OUTPUT20pF-U50HP331QA FUNCTION GENERATOR OR EQUIV1LENTSPIKE PATHRIPPLi FREQUENCY AND AMPLITUDE CONTROL100k* I !O.OIllF I ISPIKE GATING旧UF圧R74AHC042牢FDC 用 IPPLEPATH15V10pFTYP O.OIVp.pTO 0.1Vp.p RAMPSREGULATOR DC BIAS INPUT TYP 3.3V to 3.5 V-15 VLT1210□ p丄 0.01 nF 丄INLT17E3-3OUTSDGNDBYPREGULATOR UNDER TESTM1I1FK* =1% METAL FILM RESISTORL1 =4 KJRNS «6,1/4- DIAMETERFB =圧RRITE BEAD. FAJR-RIH 2743002122. INDUCTORS OPTIONAL SEE TEXT =IN41 羽C|N = SEE TEXTCqut = SEE TEXTFigure 5. Circuit Simulates Switching Regulator Output. DC, Ripple Amplitude, Frequency and Spike Duration/Height are Independantly Settable. Split Path Scheme Sums Wideband Spikes with DC and Ripple, Presenting Linear Regulator with Simulated Switching Regulator Output. Function Generator Sources Waveforms to Both Paths函数发生器产生两个同步信号，一个为Vpk可调的锯齿波，一个为同步的矩形波。

锯齿波 经过隔直后于外部的直流电压相加，然后通过A1放大输出叠加了纹波的直流电压丄1和1Q 电阻是为了让A1能够稳定的输出同步的锯齿波经过微分电路及C1、C2两个比较器后， 输出两个脉冲低电平，经过二极管的与门及反相器后，驱动Q1输出电压尖峰，经过22uF 电容叠加到LDO的输入端LT1460的输出电压，通过一个1k电位器和A2来调节电压尖峰的宽度Figure 6. Switching Regulator Output Simulator Waveforms.Function Generator Supplies Ripple (Trace A) and Spike (TraceB) Path Information. Di^erentiated Spike Information's BipolarExcursion (Trace C) is Compared by C1-C2, Resuming in Trace D and E Synchronized Spikes. Diode Gating/Enverters Present Trace F to Spike Amplitude Control. Q1 Sums Spikes with DC-Ripple Path From Power Amplifier A1, Forming Linear Regulator Input (Trace G). Spike Width Set Abnormally Wide for Photographic ClarityLinear Regulator High Frequency Rejection Evaluation/OptimizationCin=luF, Cout = 10uF,纹波抑制约为20倍，但是电压尖峰没有什么变化，仍然很高。

电容 由于寄生电感及电阻，对高频滤波没太大作用A=0.2V/DIVAC COUPLED ON 3.3VDCB = 0.01V/DIVAC COUPLED ON 3VDC500ns/DIVFigure 7. Linear Regulator Input (Trace A) and Output (Trace B) Ripple and Switching Spike Content for 師=1|uF, Cout = 1OliF. Output Spikes, Driving 10wF: Have Lower Amplitude, But Risetrme Remains Fast增大输出电容Cout = 33uF，纹波电压进一步降低，抑制比又提高了 5倍，但是对电压尖峰十衰减很少500ns.1]IVCin前加一个铁氧体磁珠，电压尖峰抑制了 5倍，直流及低频部分未衰减A = Q.2V/DIVAC COUPLED ON 3.3VDcB = 0.01V/DIV AC C。