（可编）故障模拟和测试分档.docx

AEC • Q100-007 Rev-AAutomotive Electronics CouncilComponent Technical CommitteeAEC-Q100-007 Rev-AFAULT SIMULATION AND TEST GRADINGAEC-Q100-007 Rev-A故障模拟和测试分档AEC • Q100-007 Rev-AAutomotive Electronics CouncilComponent Technical CommitteeMETHOD 一 007方法一007FAULT SIMULATION AND TEST GRADING故障模拟和测试分档Text enhancements and differences made since the last revision of this document are shown as underlined areas.卜划线区域友示上一版本后增加的文字和不同之处L PURPOSE 目的This test method defines test grading procedure and specifies a level to which the manufacturing test program for the device under test must detect faults. Parametric failures are not covered. Another term for test grading is fault simulation. Test grading applies to all digital circuits including the digital portion of mixed signal and linear circuits. Test grading does not apply to the linear portion of the circuits.该测试方法决定了测试分档程序并特别说明了到哪个 等级运行中的该测试程序必须能探测到不良。

这里不包括参数不良测试分档的另一种说法是故障模拟•测试分档可 应用于所有数字电路包括多信号和线性电路的数字部分测试分档不可应用于集成电路的线性部分Also, this document covers modeling and logic simulation requirements; the assumed fault model and fault simulation requirements; and the procedure that must be followed to evaluate and report fault coverage.同样，该文件也包含了建模和逻辑模拟要求：假定的故障模型和故障模拟要求：以及必须用「评价和报告故障栃盖的 程序2. PROCEDURE 程序2.1 Simulation 模拟Simulation is an imitative process used to study relationships between parameters that interact in an Integrated Circuit. The simulator must support at least zero (0), one (1) and unknown (X) logic states. In addition, the simulator must support appropriate “strengths” to enable correct modeling of logic based upon the target technology and design practices.模拟是一个模仿的过程，用来研究集成电路中相互影响的参数之间的关系。

模拟為必须至少支持0, 1和未知X的選 辑说明.同外，在目标技术和设计实.的基確匕 模拟器必须具有适当的能〃来纠正逻辑建模.Simulation employs models that are replica accurate enough to imitate the behavior of the circuit. Integrated circuits can be described at several levels of abstraction:模拟使用那些有者足够精确度的模型来模仿电路中的行为集成电路能在多个等级的提取中被描述a. Behavioral Model: The integrated circuit is described in terms ol the algorithm that it performs. 动作模型：集成电路根据运算法则被描述b. Functional Model: The integrated circuit is described in terms ol the How of daland 8ntrol signals within and between the functional blocks. These blocks are made of latches, registers, and elements ol similar level of complexity.功能模型，集成电路根据数据和控制信号在功能块内部和之间流■被描述。

这块足巾门锁•注増和类似的复杂元素构成的c.d.U21LLogical Model: The integrated circuit is described in terms of an interconnection of switching elements (gates and flip flops) and is also referred tas qate or structural model.逻辑模型：集成电路根据转换元素(门和触发器)的相互联络被描述.也被称为门或结构模型.AimSwitch・Level Model: The integrated circuit is described in terms1 the logical behavior of a metal oxide semiconductor circuit. A switch・level model consists ol nodes connected by transistors, also referred to as transistor model.开美级模型:集成电路根据金楣轼化半导体电路的逻辑行为被描述.一个开关级模型山许名靠品体管连接 的接点，也被称为船体管模型.Copyright 2003 by DaimlerChrysler. Delphi Delco Eieciromcs Systems, ano Visteon Corporation. This document may be freely repnnted with this copyright notice. This document cannot be changed without approval by the AEC Component Technical CommitteePagel of 12AEC - Q100-007 Rev-AAutomotive Electronics CouncilComponent Technical Committee2.1.1 Simulation Model 模拟模型A simulation model of the fault free device shall be constructed. Modeling of the device shall be at the Boolean gate level (Logical Model) and include all inputs and outputs. Modeling at the transistor level is allowable. Modeling at the register level is permissible if each register model is analyzed at the internal Boolean gate or transistor level for stuck-at-one and stuck-at-zero fault coverage with the test sequence applied to the external register nodes.构建一个无故障产品的模拟模型。

产品模型应该处于布尔门(逻辑模型)且包含所冇输入和输出品体管级 的建模是允许的寄存器水平的建模也是可以的.如果用应用在外部寄存器方式的测式顺序来对固定1和固 定0的故障进行内部布尔门或晶体管级的寄存器方式分析•2.12 Simulation Database 模拟数据库The database used for simulation shall include all gates internal to the device, including memory portions, analog sections, and high impedance buffers to the input/output pins. Behavioral models will only be allowed to model the functionality of RAMs, ROMs, EPROMs, EEPROMs, and analog sections of design. Behavioral models on other modules may be used as long as the module under consideration for fault grading is modeled at the gate level.用丁模拟的数据咋应包括所有往器件的所有门，包括记忆部分，模拟部分，和往输入/输出端的高阻抗緩存块.行 为模型只允许用「模仿RAMs, ROMs, EPROMs, EEPROMs的功能性和设计的模拟部分.只要门级中为故障 分档的模块，行•为模型也能在其他模块上使用.2.2 Fault Simulation 故障模拟Fault simulation is used to measure the effectiveness of a defined ordered set of input test vectors to detect a specified set of modeled faults in a device under test. The only relevant fault models considered in this document are discussed next.故障模拟是用来测虽一会定义好的有规则的输入测试向ht的效力从而来探测测试时该器件中的一套特定 模式的故障.唯一一个被考晦进这份文件的相关的故障模式就是接下来要讨论的.2.2.1 Single Stuck-at Fault Model 单一固定故障模式A fault is defined as a single, stuck-at one (SA1) or stu。