状态机设计程序代码.doc

module fsm_ctrl(clk,rst,start,step_a,step_b,out_sig);input clk ;input rst ;input start ;input [1:0] step_a ;input [1:0] step_b; output [2:0] out_sig ;reg [2:0] out_sig ;reg [1:0] state ;reg [1:0] next_state;parameter IDLE = 2’b00, S1=2’b01,S2=2’b10,S3=2’b11;always @(posedge clk or posedge rst) beginif(rst == 1’b1) beginstate <= IDLE;endelse beginstate <= next_state ;endendalways @(state or start or step_a or step_b)begincase(state)IDLE: beginif(start) next_state <= S1;else next_state <= IDLE;endS1: beginnext_state <= S2;endS2: beginif(step_a == 2’b10) next_state <= S3;else next_state <= S0;endS3: beginif(step_b == 2’b11) next_state <= S0;else next_state <= S3;enddefault: next_state <= IDLE;endcaseendalways @(state)begincase(state)IDLE: out_sig = 3’b001;S1 : out_sig = 3’b010;S2 : out_sig = 3’b101;S3 : out_sig = 3’b111;endcaseend。