VHDL编写一位全加器参考程序.doc

这是茄子求别人写的参考程序，不一定能实际运行但是可靠性在百分之九十左右大家做不出来的可以参考下做出来的看出错误请指正我作为学习委员既然把答案给大家，一方面是不想影响大家平时成绩，另一方面也是希望大家可以自己看看，学习一下，不要到最后结课了着急所以我晚上不收打印的作业，每个人都必须亲自抄写出来行为描述方式LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADD11 IS PORT(A:IN STD_LOGIC; B:IN STD_LOGIC; CIN:IN STD_LOGIC; CO:OUT STD_LOGIC; S:OUT STD_LOGIC);END ADD11;ARCHITECTURE BEHAVE OF ADD11 ISBEGIN PROCESS(A,B,CIN) VARIABLE N: INTEGER RANGE 0 TO 3; CONSTANT S_VECTOR: STD_LOGIC_VECTOR(0 TO 3):="1010"; CONSTANT CO_VECTOR: STD_LOGIC_VECTOR(0 TO 3):="1100"; BEGIN N:=0; IF(A='1') THEN N:=N+1; END IF; IF(B='1') THEN N:=N+1; END IF; IF(CIN='1') THEN N:=N+1; END IF; S<=S_VECTOR(N); CO<=CO_VECTOR(N); END PROCESS;END BEHAVE;数据流描述方式LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADD2 IS PORT(A:IN STD_LOGIC; B:IN STD_LOGIC; CIN:IN STD_LOGIC; CO:OUT STD_LOGIC; S:OUT STD_LOGIC);END ADD2;ARCHITECTURE DATAFLOW OF ADD2 ISSIGNAL TMP1,TMP2:STD_LOGIC;BEGIN TMP1<=A XOR B; TMP2<=TMP1 AND CIN; S<=TMP1 XOR CIN; CO<=TMP2 OR(A AND B); END DATAFLOW;结构体描述方式LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADD3 IS PORT(A:IN STD_LOGIC; B:IN STD_LOGIC; CIN:IN STD_LOGIC; CO:OUT STD_LOGIC; S:OUT STD_LOGIC);END ADD3;ARCHITECTURE STRUCTURE OF ADD3 IS COMPONENT AND2 PORT(A: IN STD_LOGIC; B: IN STD_LOGIC; C: OUT STD_LOGIC); END COMPONENT; COMPONENT OR2 PORT(A: IN STD_LOGIC; B: IN STD_LOGIC; C: OUT STD_LOGIC); END COMPONENT; COMPONENT XOR2 PORT(A: IN STD_LOGIC; B: IN STD_LOGIC; C: OUT STD_LOGIC); END COMPONENT; SIGNAL TMP1,TMP2,TMP3:STD_LOGIC;BEGIN U1:XOR2 PORT MAP(A,B,TMP1); U2:AND2 PORT MAP(TMP1,CIN,TMP2); U3:XOR2 PORT MAP(TMP1,CIN,S); U4:AND2 PORT MAP(A,B,TMP3); U5:OR2 PORT MAP(TMP2,TMP3,CO);END STRUCTURE; 。