ISE约束UCF编辑的操作介绍.doc

摘要：本文主要通过一个实例具体介绍 ISE 中通过编辑 UCF 文件来对 FPGA 设计进行约束，主要涉及到的约束包括时钟约束、群组约束、逻辑管脚约束以及物理属性约束Xilinx FPGA 设计约束的分类Xilinx 定义了如下几种约束类型：• “Attributes and Constraints”• “CPLD Fitter”• “Grouping Constraints”• “Logical Constraints”• “Physical Constraints”• “Mapping Directives”• “Placement Constraints”• “Routing Directives”• “Synthesis Constraints”• “Timing Constraints”• “Configuration Constraints”通过编译 UCF（user constraints file）文件可以完成上述的功能还是用实例来讲 UCF 的语法是如何的图 1 RTL Schematic图 1 是顶层文件 RTL 图，左侧一列输入，右侧为输出，这些端口需要分配相应的FPGA 管脚。

1: NET "pin_sysclk_i" LOC = AD12 | TNM_NET = pin_sysclk_i;2: TIMESPEC TS_pin_sysclk_i = PERIOD "pin_sysclk_i" 15 ns HIGH 50 %;3: #4: NET "pin_plx_lreset_n_i" LOC = B18;5: #6: NET "pin_plx_lhold_i" LOC = C17;7: NET "pin_plx_lholda_o" LOC = D17 | SLEW = FAST;8: #9: NET "pin_plx_ads_n_i" LOC = E18;10: NET "pin_plx_ads_n_i" OFFSET = IN 6.3 ns AFTER "pin_sysclk_i" HIGH;11: #12: NET "pin_plx_lw_r_n_i" LOC = E9;13: NET "pin_plx_lw_r_n_i" OFFSET = IN 6.3 ns AFTER "pin_sysclk_i" HIGH;14: #15: NET "pin_plx_blast_n_i" LOC = D18;16: NET "pin_plx_blast_n_i" OFFSET = IN 6.3 ns AFTER "pin_sysclk_i" HIGH;17: #18: NET "pin_plx_lad_io" LOC = AD13 | SLEW = FAST | TNM = LAD;19: NET "pin_plx_lad_io" LOC = AC13 | SLEW = FAST | TNM = LAD;20: NET "pin_plx_lad_io" LOC = AC15 | SLEW = FAST | TNM = LAD;21: NET "pin_plx_lad_io" LOC = AC16 | SLEW = FAST | TNM = LAD;22: NET "pin_plx_lad_io" LOC = AA11 | SLEW = FAST | TNM = LAD;23: NET "pin_plx_lad_io" LOC = AA12 | SLEW = FAST | TNM = LAD;24: NET "pin_plx_lad_io" LOC = AD14 | SLEW = FAST | TNM = LAD;25: NET "pin_plx_lad_io" LOC = AC14 | SLEW = FAST | TNM = LAD;26: NET "pin_plx_lad_io" LOC = AA13 | SLEW = FAST | TNM = LAD;27: NET "pin_plx_lad_io" LOC = AB13 | SLEW = FAST | TNM = LAD;28: NET "pin_plx_lad_io" LOC = AA15 | SLEW = FAST | TNM = LAD;29: NET "pin_plx_lad_io" LOC = AA16 | SLEW = FAST | TNM = LAD;30: NET "pin_plx_lad_io" LOC = AC11 | SLEW = FAST | TNM = LAD;31: NET "pin_plx_lad_io" LOC = AC12 | SLEW = FAST | TNM = LAD;32: NET "pin_plx_lad_io" LOC = AB14 | SLEW = FAST | TNM = LAD;33: NET "pin_plx_lad_io" LOC = AA14 | SLEW = FAST | TNM = LAD;34: NET "pin_plx_lad_io" LOC = D12 | SLEW = FAST | TNM = LAD;35: NET "pin_plx_lad_io" LOC = E13 | SLEW = FAST | TNM = LAD;36: NET "pin_plx_lad_io" LOC = C16 | SLEW = FAST | TNM = LAD; 37: NET "pin_plx_lad_io" LOC = D16 | SLEW = FAST | TNM = LAD;38: NET "pin_plx_lad_io" LOC = D11 | SLEW = FAST | TNM = LAD;39: NET "pin_plx_lad_io" LOC = C11 | SLEW = FAST | TNM = LAD;40: NET "pin_plx_lad_io" LOC = E14 | SLEW = FAST | TNM = LAD;41: NET "pin_plx_lad_io" LOC = D15 | SLEW = FAST | TNM = LAD;42: NET "pin_plx_lad_io" LOC = D13 | SLEW = FAST | TNM = LAD;43: NET "pin_plx_lad_io" LOC = D14 | SLEW = FAST | TNM = LAD;44: NET "pin_plx_lad_io" LOC = F15 | SLEW = FAST | TNM = LAD;45: NET "pin_plx_lad_io" LOC = F16 | SLEW = FAST | TNM = LAD;46: NET "pin_plx_lad_io" LOC = F11 | SLEW = FAST | TNM = LAD;47: NET "pin_plx_lad_io" LOC = F12 | SLEW = FAST | TNM = LAD;48: NET "pin_plx_lad_io" LOC = F13 | SLEW = FAST | TNM = LAD;49: NET "pin_plx_lad_io" LOC = F14 | SLEW = FAST | TNM = LAD;50: TIMEGRP "LAD" OFFSET = IN 6.4 ns AFTER "pin_sysclk_i" HIGH;51: TIMEGRP "LAD" OFFSET = OUT 3.1 ns BEFORE "pin_sysclk_i" HIGH;52: #53: NET "pin_plx_ready_n_o" LOC = F18 | SLEW = FAST;54: NET "pin_plx_ready_n_o" OFFSET = OUT 4.2 ns BEFORE "pin_sysclk_i" HIGH;55: #56: NET "pin_plx_bterm_n_o" LOC = D10 | SLEW = FAST;57: NET "pin_plx_bterm_n_o" OFFSET = OUT 4.2 ns BEFORE "pin_sysclk_i" HIGH;58: #59: NET "pin_led_o" LOC = D22;60: NET "pin_led_o" LOC = C22;61: NET "pin_led_o" LOC = E21;62: NET "pin_led_o" LOC = D21;63: NET "pin_led_o" LOC = C21;64: NET "pin_led_o" LOC = B24;65: NET "pin_led_o" LOC = C20;66: NET "pin_led_o" LOC = B23;表 1. UCF example对上面的 UCF 文件进行一些注释：该 UCF 文件主要是完成了管脚的约束、时钟的约束，以及组的约束。

第一、二行：主要定义了时钟以及对应的物理管脚第一行，端口 pin_sysclk_i 分配到 FPGA 管脚 AD12，并放到了 pin_sysclk_i group 中那如何得知是 AD12 的管脚呢，请看图 2，FPGA 管脚 AD12 是一个66MHz 的外部时钟FPGA 的开发板肯定有电路原理图供你分配外部管脚图 2，电路原理图第二行：时钟说明：周期 15ns，占空比 50%关键词 TIMESPEC（Timing Specifications），即时钟说明一般的语法是：TIMESPEC "TSidentifier"=PERIOD "timegroup_name" value [units];其中 TSidentifier 用来指定 TS（时钟说明）的唯一的名称第七行：pin_plx_lholda_o 连接至物理管脚 D17，并配置该管脚电平变化的速率关键词：SLEW，用来定义电平变化的速率的，一般语法是：NET "top_level_port_name" SLEW="value";其中 value = {FAST|SLOW|QUIETIO}, QUIETIO 仅用在 Spartan-3A。

第十行：定义 pin_plx_ads_n_i 输入跟时钟的关系OFFSET IN 和 OFFSET OUT 的约束OFFSET IN 定义了数据输入的时间和接收数据时钟沿（capture Edge）的关系一般的语法是：OFFSET = IN value VALID value BEFORE clockOFFSET = OUT value VALID value AFTER clock图 3 时序图（ OFFSET IN）例子：NET "SysCLk" TNM_NET = "SysClk";TIMESPEC "TS_SysClk" = PERIOD "SysClk" 5 ns HIGH 50%;OFFSET = IN 5 ns VALID 5 ns BEFORE "SysClk";上面的定义了基于 SysClk 的全局 OFFSET IN 的属性时序可看图 3.图 4 时序图（ OFFSET OUT）例子：NET "ClkIn" TNM_NET = "ClkIn";OFFSET = OUT 5 ns AFTER "ClkIn";上面设置主要是定了了时钟跟数据的时间关系，时序图 4可以看到这时一种全局定义，Data1 和 Data2 输出时间都受到 OFFSET = OUT 5 ns AFTER "ClkIn" 的约束。

如果需要单独定义输出端口的 OFFSET OUT 的，需要制定相应的 NET，可参考表 1 中的第 57 行第 18 至 49 行：pin_plx_lad_io 被归到了名称为 LAD 的 TM。