
锁相技术译文翻译.doc
6页锁相技术译文翻译锁相技术译文翻译英文原文:英文原文:AnAn On-ChipOn-Chip All-DigitalAll-Digital MeasurementMeasurement CircuitCircuit toto CharacterizeCharacterize Phase-LockedPhase-Locked LoopLoop ResponseResponse inin 45-nm45-nm SOISOI 译文:译文: 4545 纳米纳米 SOISOI 全数字片上测量电路表征锁相环响应特性全数字片上测量电路表征锁相环响应特性 年级专业:年级专业: 姓名:姓名: 学号:学号: 20132013 年年 6 6 月月 2 2 日日第 2 页/共 6 页英文英文中文中文AnAn On-ChipOn-Chip All-All- DigitalDigital MeasurementMeasurement CircuitCircuit toto CharactCharact erizeerize Phase-Phase- LockedLocked LoopLoop ResponseResponse inin 45-nm45-nm SOISOI AbstractAbstract——An all-digital measurement Circuit , built in 45-nm SOI- CMOS enables on- chip characterization of phase- locked loop (PLL) response to a self- induced phase step. This technique allows estimation of PLL closed- loop bandwidth and jitter peaking. Th e circuit can be used to plot step- response vs.time, measure static phaseerror, and observe phase- lock status. INTRODUCTIONINTRODUCTION Many applications such as PCI Express™require a PLL to produce alow- jitter clock at a given frequency whil e meeting stringent bandwidth and jitt er peaking requirements. Process, volt age, and temperature (PVT) variations as well as random device mismatch makeit difficult to guarantee a narrow ra nge for PLL response. For example ,loop parameters such as VCO gain could vary by more than 2X over PVT corners. In Fig. 1, we see the clo sed- loop jitter transfer functions of two PLLs with identical reference clock an d output frequencies. One PLL exhibi ts large peaking and low bandwidth whi le the other shows little peaking but high bandwidth. Although differences i n this example are more extreme than u sual, similar but smaller differences often result from PVT variations. 4545 纳米纳米 SOISOI 全数字片上测量电路表征锁相环全数字片上测量电路表征锁相环 响应特性响应特性摘要---建立在 45 纳米的 SOI-CMOS 上一个 全数字测量电路,它能够表征 PLL 对自诱导 相步进的响应这项技术允许对 PLL 闭环带宽和抖动峰值的 估计。
这个电路被用来绘制阶跃响应随时间 变化的曲线,测量静态相位误差和观察相位 锁定状态介绍 很多应用例如 PCI Express™需要一个 PLL 来 产生一个低抖动的在一个给定频率的时钟, 这个频率满足精确带宽和抖动峰值的要求工艺,电压,和温度(PVT)变化以及随机 的选择不搭配的器件都使得很难保证一个窄 的变化范围的 PLL 响应,例如,环路参数如 VCO 增益变化可能超过 PVT 角 2 倍上以 图一中,我们可以看到两个具有相同参考时 钟和输出频率 PLL 的闭环抖动传递函数一个 PLL 展现大的峰值和低带宽,而另一个 展示了小峰值但是高带宽虽然这个例子中显示的差异比通常的要极端, 这种相似会随着 PVT 的变化而变小PLL 的响应往往使用一个信号发生器、示波第 3 页/共 6 页PLL response is often measured on atest bench using signal generators, o scilloscopes, and/or spectrum analyzer s. For example, the transfer functio ns in Fig. 1 were automatically genera ted by modulating the 100- MHz reference clock with various frequ encies while observing the amplitudes of the resulting output spurs. Such me thods, which may require many seconds to complete, motivate the need for fa ster, less expensive, and preferably o n- chip techniques to characterize PLL re sponse [1]- [3]. Fig. 2 shows the PLL output phas e transient response to an induced pha se step. Similar to other second- order feedback systems, the PLL tends to overcorrect (or overshoot) as it wo rks to eliminate the induced phase err or. If the PLL is underdamped, as in t his example, the PLL may ring several times before settlingto its final lockstate. A key metric in the PLL step- response is crossover, defined here asthe elapsed time from input step toonset o f phase overshoot. Another key metric is MaxOvershoot. It measures the maximum overcorrectionin the step response. Transient simulations and closed- form loop equations [4] show that cros sover is inversely proportional to thePLL’s 3dB closed- loop bandwidth; the smaller crossoveri s, the higher the bandwidth (Fig. 3). Notice that crossover is largely indep endent of the size ofthe phase step. B oth simulations and loop equations als o predict that MaxOvershoot is proport ional to the maximum peaking in the cl osed-器,和/或频谱分析仪。
例如,在图一中传递函数是通过调制 100MHz 能产生各种频率的参考时钟同时观察输出马刺产生的幅值自动生成的 这种方法,可能需要一些时间去完成,这促 进了更快,更便宜的方法的需要比较好的方法是片上系统来表征 PLL 的响应 特性[1]-[3] 表二表明致相步进响应的输出瞬态相位类似于其他二阶反馈系统,PLL 倾向于过调 (或过调) ,那是因为它是为了消除相位误 差如果锁相环工作在欠阻尼状态,在这种状态 下,PLL 可能要经过几次锁存在达到最终锁 存状态之前 锁相环阶跃响应的一个关键指标是交叉反应在此定义为从输入步进到相位超调开始出现 所用的时间 另一个关键指标是最大超调量它可以测量 阶跃响应的最大过调量瞬态模拟和闭环回路方程[4]表明交叉反应 和 PLL 的 3dB 闭环带宽成反比;交叉反应越小,带宽越大(图 3) 请注意,交叉反应在很大程度上与相位步长 无关 模拟和回路方程还预测到闭环传递函数中最 大超调与最大峰值是成正比的;第 4 页/共 6 页loop transfer function; the larger Max Overshoot is, the greater the peaking (Fig. 4). Notice thatthe m agnitude of the overshoot isalso propo rtional to theinput stepsize .These relationships between time-and frequency- domain behaviors allow us to make fasttime- domain measurements and then relate th e results back to frequency- domain performance specifications. The circuit implementation presented in this papershows that the PLL step response ma y be captured by anall-digital, on- chip finite statemachine, allowing forfast PLL characterization. Silicon re sults indicate that this circuit couldallow for Power- on calibration of the PLL bandwidth an d peaking for compensation of process variations. CIRCUITCIRCUIT DESIGNDESIGN The PLL und。
