I2C通讯协议(英文原版)I2C_Spec_en.pdf

THE I 2C BUS SPECIFICATION VERSION 2 1 JANUARY 2000 document order number 9398 393 40011 2 Philips Semiconductors The I2C bus specification CONTENTS 1PREFACE 3 1 1Version 1 0 1992 3 1 2Version 2 0 198 3 1 3Version 2 1 1999 3 1 4Purchase of Philips I2C bus components 3 2THE I2C BUS BENEFITS DESIGNERS AND MANUFACTURERS 4 2 1Designer benefits 4 2 2Manufacturer benefits 6 3INTRODUCTION TO THE I2C BUS SPECIFICATION 6 4THE I2C BUS CONCEPT 6 5GENERAL CHARACTERISTICS 8 6BIT TRANSFER 8 6 1Data validity 8 6 2START and STOP conditions 9 7TRANSFERRING DATA 10 7 1Byte format 10 7 2Acknowledge 10 8ARBITRATION AND CLOCK GENERATION 11 8 1Synchronization 11 8 2Arbitration 12 8 3Use of the clock synchronizing mechanism as a handshake 13 9FORMATS WITH 7 BIT ADDRESSES 13 107 BIT ADDRESSING 15 10 1Definition of bits in the first byte 15 10 1 1General call address 16 10 1 2START byte 17 10 1 3CBUS compatibility 18 11EXTENSIONS TO THE STANDARD MODE I2C BUS SPECIFICATION 19 12FAST MODE 19 13Hs MODE 20 13 1High speed transfer 20 13 2Serial data transfer format in Hs mode 21 13 3Switching from F S to Hs mode and back 23 13 4Hs mode devices at lower speed modes 24 13 5Mixed speed modes on one serial bus system 24 13 5 1F S mode transfer in a mixed speed bus system 25 13 5 2Hs mode transfer in a mixed speed bus system 25 13 5 3Timing requirements for the bridge in a mixed speed bus system 27 1410 BIT ADDRESSING 27 14 1Definition of bits in the first two bytes 27 14 2Formats with 10 bit addresses 27 14 3General call address and start byte with 10 bit addressing 30 15ELECTRICAL SPECIFICATIONS AND TIMING FOR I O STAGES AND BUS LINES 30 15 1Standard and Fast mode devices 30 15 2Hs mode devices 34 16ELECTRICAL CONNECTIONS OF I2C BUS DEVICES TO THE BUS LINES 37 16 1Maximum and minimum values of resistors Rp and Rs for Standard mode I2C bus devices 39 17APPLICATION INFORMATION 41 17 1Slope controlled output stages of Fast mode I2C bus devices 41 17 2Switched pull up circuit for Fast mode I2C bus devices 41 17 3Wiring pattern of the bus lines 42 17 4Maximum and minimum values of resistors Rp and Rs for Fast mode I2C bus devices 42 17 5Maximum and minimum values of resistors Rp and Rs for Hs mode I2C bus devices 42 18BI DIRECTIONAL LEVEL SHIFTER FOR F S MODE I2C BUS SYSTEMS 42 18 1Connecting devices with different logic levels 43 18 1 1Operation of the level shifter 44 19DEVELOPMENT TOOLS AVAILABLE FROM PHILIPS 45 20SUPPORT LITERATURE 46 3 Philips Semiconductors The I2C bus specification 1PREFACE 1 1Version 1 0 1992 This version of the 1992 I2C bus specification includes the following modifications Programming of a slave address by software has been omitted The realization of this feature is rather complicated and has not been used The low speed mode has been omitted This mode is in fact a subset of the total I2C bus specification and need not be specified explicitly The Fast mode is added This allows a fourfold increase of the bit rate up to 400 kbit s Fast mode devices are downwards compatible i e they can be used in a 0 to 100 kbit s I2C bus system 10 bit addressing is added This allows 1024 additional slave addresses Slope control and input filtering for Fast mode devices is specified to improve the EMC behaviour NOTE Neither the 100 kbit s I2C bus system nor the 100 kbit s devices have been changed 1 2Version 2 0 1998 The I2C bus has become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies Many of today s applications however require higher bus speeds and lower supply voltages This updated version of the I2C bus specification meets those requirements and includes the following modifications The High speed mode Hs mode is added This allows an increase in the bit rate up to 3 4 Mbit s Hs mode devices can be mixed with Fast and Standard mode devices on the one I2C bus system with bit rates from 0 to 3 4 Mbit s The low output level and hysteresis of devices with a supply voltage of 2 V and below has been adapted to meet the required noise margins and to remain compatible with higher supply voltage devices The 0 6 V at 6 mA requirement for the output stages of Fast mode devices has been omitted The fixed input levels for new devices are replaced by bus voltage related levels Application information for bi directional level shifter is added 1 3Version 2 1 2000 Version 2 1 of the I2C bus specification includes the following minor modifications After a repeated START condition in Hs mode it is possible to stretch the clock signal SCLH see Section 13 2 and Figs 22 25 and 32 Some timing parameters in Hs mode have been relaxed see Tables 6 and 7 1 4Purchase of Philips I2C bus components Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips 4 Philips Semiconductors The I2C bus specification 2THE I2C BUS BENEFITS DESIGNERS AND MANUFACTURERS In cons