留学生Essay写作—触发器电路的说明和研究

1、http:/ 留学生论文专业定制代写网站留学生Essay写作触发器电路的说明和研究A flip-flop is a term referring to an electronic circuit(a bistable multivibrator)that has two stable states and thereby is capable of serving as one bit of memory.Today,the term flip-flop has come to mostly denote non-transparent(clocked or edge-triggered)devices,while the simpler transparent ones are often referred to as latches;however,as this distinction is quite new,the two words are sometimes used interchangeably.A flip-flop is usually controlled by

2、 one or two control signals and/or a gate or clock signal.The output often includes the complement as well as the normal output.As flip-flops are implemented electronically,they require power and ground connections.IntroductionBasic Flip-Flop CircuitA flip-flop circuit can be constructed from two NAND gates or two NOR gates.Each flip-flop has two outputs,Q and Q,and two inputs,set and reset.This type of flip-flop is referred to as an SR flip-flop or SR latch.The flip-flop in figure has two usefu

3、l states.When Q=1 and Q=0,it is in the set state(or 1-state).When Q=0 and Q=1,it is in the clear state(or 0-state).The outputs Q and Qare complements of each other and are referred to as the normal and complement outputs,respectively.The binary state of the flip-flop is taken to be the value of the normal output.When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2,both Q and Qoutputs go to 0.This condition violates the fact that both outputs are complements of each o

4、ther.In normal operation this condition must be avoided by making sure that 1s are not applied to both inputs simultaneously.The NAND basic flip-flop circuit in figure operates with inputs normally at 1 unless the state of the flip-flop has to be changed.A 0 applied momentarily to the set input causes Q to go to 1 and Qto go to 0,putting the flip-flop in the set state.When both inputs go to 0,both outputs go to 1.This condition should be avoided in normal operation.Master-Slave Flip-FlopIntroduc

5、tionA master-slave flip-flop is constructed from two seperate flip-flops.One circuit serves as a master and the other as a slave.The logic diagram of an SR flip-flop is shown in figure.The master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter.The information at the external R and S inputs is transmitted to the master flip-flop.When the pulse returns to 0,the master flip-flop is disabled and the slave flip-flop is enabled.The sl

6、ave flip-flop then goes to the same state as the master flip-flop.In addition to these two flip-flops,the circuit also includes an inverter.The inverter is connected to clock pulse in such a way that the inverted CP is given to the slave flip-flop.For example,if the CP=0 for a master flip-flop,then the output of the inverter is 1,and this value is assigned to the slave flip-flop.In other words if CP=0 for a master flip-flop,then CP=1 for a slave flip-flop.A master-slave flip flop can be construc

7、ted using any type of flip-flop which forms a combination with a clocked RS flip-flop,and with an inverter as slave circuit.An RS master-slave flip-flop consists of two RS flip-flops;one is the master flip-flop and the other a slave.The inverted CP is given to the slave flip-flop.Now when CP=0,the master flip-flop is disabled.So the external inputs R and S of the master flip-flop will not affect the circuit until CP goes to 1.The inverter output goes to 1 and it enables the slave flip-flop.The o

8、utput Q=Y and Q=Y.When CP=1,the master flip-flop is enabled and the slave flip-flop remains isolated from the circuit until CP goes back to 0.Now Y and Ydepends on the external inputs R and S of the master flip-flop.Assume that the flip-flop is in a clear state and no clock pulse is applied to the circuit.The external inputs given are S=1 and R=0.This input will not affect the state of the system until the CP=1.Now the next clock pulse applied should change the state to SET state(S=1,R=0).During

9、 the clock pulse transition from 0 to 1,the master flip-flop goes to set state and changes the output Y to 1.However this does not affect the output of the system since the slave flip-flop is isolated from the system(CP=0 for slave).So no change is observed at the output of the system.When the CP returns to 0,the master flip-flop is disabled while the slave is enabled.So the information from the master is allowed to pass through to the slave.Since Y=1,this changes the output Q to 1.In a master slave flip-flop it is possible to change the output of the flip-flop and the external input with same clock pulse.This is because the external input S can be changed at the same time while the pulse goes through its negative edge transition.When CP=0,change in external input S would not affect the state of the system.From this behavior of the master slave flip-flop it is quite clear that the state change

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