c note x40 power on sequence
67页1、30-Sep , 2003 Charles YM Chen NB Product Engineering,S Note Power Sequence Presentation,S Note Block Diagram,S Note Power on Sequence,MAX1977,MAX1845,MAX1907,MAX1992,Fuse 7A,FET Pch,FET Pch,FET Nch,FET Nch,DC-IN Connector,Docking Connector,VINT16,Tsurumai,VCC3SW,VCCCPUCORE,FET Nch,FET Nch,LP3958,Fuse 0.75A,FET Pch,VCC_FAN,VCC5B,VCC5M,USB_PWR1,USB_PWR2,MICVCC,VCC2R5A,FET Nch,VCC3B,VCC3M,FET Pch,VCC3AUX,VCC3P,Fuse 2A,FET Nch,VBL16,Fuse 2A,VCCCPUIO,VCC1R5M,FET Nch,FET Nch,FET Nch,VCC1R5B,VCC1R5AUX,
2、FET Nch,VCCGBEIOAUX,VCC1R8M,(Kenai2-32),For Ethernet Controller,PolySW 1.5A,VDD15,H8,VCC1R25B,LP2996,MAX4245,VCCGMCHCORE,MAX1845_VREF,MAX1683,FET Nch,PolySW 1.5A,MAX8880,VCCACPU,MAX1935,VCC1R8M,MAX1935,VCC3M,VCCGBECOREAUX,ICH4M,PMH4,CPU,PWRSWITCH#,PWRSW_H8#,PWRSW_H8#,Power Button,PWRSW#,ICH_SLP_S3#,ICH_SLP_S4#,ICH_SLP_S4#,ICH_SLP_S3#,PM_SLP_S3#,PM_SLP_S5#,VTT_PWRG,VTT_PWRG,VR_PWRGD,VR_PWRGD,PCIRST#,PWRBTN#,SLP_S3#,SLP_S4#,+PWRON,B_ON,VCPU_CORE_ON,DDR_VREF,MPWRG,APWRG,BPWRG,PCIRST#,CC_CPUPWRGD,CC
3、_CPUPWRGD,PWRGOOD,GTL_CPURST#,GTL_CPURST#,GTL_ADS#,MONTARA GM+,CPURST#,BPWRG,PWROK,IM VPOK,DOCK-PWR16_F,1,2,VREGIN16,2,3,4,4,4.1,4,4,5,5,6,6,6,6,7,7,7,7,7,8,8,8,9,5,5,10,10,10,10,11,11,11,11,11,12,12,13,14,15,16,17,18,19,MPWRG,BPWRG,PWROK,RSMRST#,Power on seuqence table,Power on seuqence table,DOCK-PWR16_F & VREGIN 16,VCC3SW,VCC3M_ON & VCC5M_ON,Spec: VCC3M_ON(M_ON1) to VCC5M_ON(M_ON2) is 10ms20ms,VCC3M & VCC5M,VCC3M & VCC%M power by MAXIM 1977,VCC3M & VCC5M,VCC1R5M & VCC1R8M,VCC1R5M power by MAX
4、IM 1845,VCC1R8M power by MAXIM 1935,VCC1R5M & VCC1R8M,MPWRG,In the block of M_PGS, the voltage of VCC5M and VCC3M are monitored by the internal analog comparator respectively, each state is supplied to M_PGS output. The terminal is Open drain structure. The operation of detection is started when both 5M_ON and 3M_ON are equal to High. The analog Comparator has hysteresis voltage and generate high signal when the following condition are satisfied. Greater than 4.461V(Typ.) at power on stage of VC
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