Modelsim仿真risk cpu

1、. . 实验报告分组信息：组长成员一， 实验容CPU的验证，使用cpu_test.v作为测试程序。其子模块包括寄存器，计数器，存储器，多路选择器，时序控制，算术逻辑单元等的设计二， 实验目的用诊断程序作为激励，在子模块全部完成的情况下，测试所设计的CPU三， 实验工具本次试验中，使用两个软件平台：Quartus II 11.0和Modelsim SE 10.2c四， 实验说明我们在本次实验中，采用的仿真方法是结合Quartus II和Modelsim两个软件。因为对于代码较杂，需引入较多外部测试文件的工程而言，ModelSim的响应时间长，窗口初始化慢。结合使用两个软件，可在Quartus II中调用ModelSim软件。Quartus II作为FPGA的软件平台，在建立大型工程方面自然有ModelSim无法比拟的优势。在Quartus II中编写代码可以很方便地进行编译查错，生成对应的模块，在.bdf文件中进行模块的连线或者在.v文件中进行实例化等，而且Quartus II本身提供逻辑分析仪，也可以脱离ModelSim进行初步的波形仿真和校验。因而本实验中，我们采用的两个软件相结合的

2、仿真方法。模块名Alu设计测试模块说明：1ALU 端口信息如上面的电路图；2ALU 的设计同时还要满足下面的规则：模块名为alu;ALU 为组合逻辑，输入变化立刻就会引起输出的相应变化。操作码和操作数的变化会引起信号alu_out 的变化，中间有3.5ns 的延迟。操作码为3 位，功能如下：Opcode : ALU Operation000 : pass accumulator001 : pass accumulator010 : ADD (data + accumulator)011 : AND (data & accumulator)100 : XOR (data accumulator)101 : pass data110 : pass accumulator111 : pass accumulator操作码为X 时，ALU 的输出也为不定态。累加器accum 的变化会引起零标志位（zero）的变化，中间有1.2ns 的延迟。当累加器为0 时zero = 1,其他情况为0。设计代码：timescale 1ns / 100psmodule alu(alu_out, zero, op

3、code, data, accum); input 7:0 data, accum; input 2:0 opcode; output 7:0 alu_out; reg 7:0 alu_out; output zero; reg zero; always (data or accum or opcode) casez(opcode) 3b000: #3.5 alu_out=accum; 3b001: #3.5 alu_out=accum; 3b010: #3.5 alu_out=accum+data; 3b011: #3.5 alu_out=accum&data; 3b100: #3.5 alu_out=accumdata; 3b101: #3.5 alu_out=data; 3b110: #3.5 alu_out=accum; 3b111: #3.5 alu_out=accum; default: #3.5 alu_out=bx; endcase always (accum) if(accum=0) #1.2 zero=1b1; else #1.2 zero=1b0;endmodul

4、e测试代码如下：timescale 1ns / 1nsmodule alu_test; wire 7:0 alu_out; reg 7:0 data, accum; reg 2:0 opcode; integer i, err_cnt;/ Instantiate the ALU. Named mapping allows the designer to have freedom/ with the order of port declarations alu alu1 (.alu_out(alu_out), .zero(zero), /outputs from ALU .opcode(opcode), .data(data), .accum(accum); /inputs to ALU /define mnemonics to represent opcodes define PASSA 3b000, 3b001, 3b110, 3b111 define ADD 3b010 define AND 3b011 define XOR 3b100 define PASSD 3b101/ De

5、fine a safe delay between each strobing of the ALU inputs/outputs define strobe 20 initial begin / SET UP THE OUTPUT FORMAT FOR THE TEXT DISPLAY $display(ttt INPUTS OUTPUTS n); $display(ttt OPCODE DATA IN ACCUM IN | ALU OUT ZERO BIT); $display(ttt - - - | - -); $timeformat(-9, 1, ns, 9); /Display time in nanoseconds err_cnt = 0; / APPLY STIMULUS TO THE INPUT PINS accum = 8hDA; /Initialize inputs to the ALU data = 8h37; for (i = 0; i = 7; i = i+1) /VERIFY OPERATION FOR ALL 8 OPCODES begin /change

6、 inputs at strobe point #strobe opcode = i; /Wait for ALU to process inputs #(strobe/4) check_outputs; /call a task to verify outputs end /VERIFY OPERATION WITH UNKNOWN OPCODE #(3*strobe/4) opcode = 3b00x; #(strobe/4) check_outputs; /VERIFY OPERATION OF ZERO BIT #(3*strobe/4) accum = 8h00; opcode = ADD; #(strobe/4) check_outputs; /WAIT 1 MORE STROBE AND THEN FINISH #strobe if (err_cnt) $display(nThere were %d errors in all.n, err_cnt); else $display(nNo errors were found!n); $finish; end task ch

7、eck_outputs; casez (opcode) PASSA : begin $display(PASS ACCUM OPERATION:, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != accum) | (zero != !accum) error; end ADD : begin $display(ADD OPERATION :, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != (accum + data) | (zero != !accum) error; end AND : begin $display(AND OPERATION :, %b %b %b | %b %b, opcode, data, accum, alu_out, zero); if (alu_out != (accum & data) | (zero != !accum) error; end XOR : begin $display(XOR OPERATION :, %b %b %b | %b %b, opcode, data, accum, alu_out, zero);

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