AltiumDesigner设计教程19

1、DB31 Altera Cyclone II F672第一部分 原理图目录树1 DB31_TOP.SchDoc1.1 PSU.SchDoc1.1 PSU_MAX1831.SchDoc1.2 DB31_Hardware_Kit.SchDoc1.2. DB_MOUNTS.SchDoc1.3 DB_ByPass.SchDoc1.4 DB_Common.SchDoc1.4.1 DEVICES.SchDoc1.4.1.1 FPGA.SchDoc1.4.1.1.1 FPGA_NonIO.SchDoc1.4.1.1.2 Bypass_FPGA_1V2.SchDoc1.4.1.1.3 Bypass_FPGA_1V3.SchDoc1.4.1.1.4 1WB_DS2406_EPROM.SchDoc1.4.2 NB2_CommonMemory_Terminaiton.SchDoc1.4.3 DB_LEDS.SchDoc1.4.4 NB2_CommonMemory.SchDoc1.4.4.1 FLASH_S29GL256N11FF1V10_16M16.SchDoc1.4.4.2 SDRAM_MT48LC16M

2、16A2TG_16M32.SchDoc1.4.4.3 SRAM_256K32_TSOP44_1.SchDoc1.4.5 MotherBooardConnectors.SchDoc1.4.6 SRAM_256K16_TSOP44.SchDoc1.5 DB31.PcbDoc1.6 DB31_Panel.PcbDoc第一部分 原理图1 DB31_TOP.SchDocU_DB_CommonDB_CommonU_ PSUPSU.SCHDOCU_Bypass_Board DB_BypassU_DB31_Hardware_KitDB31_Hardware_Kit.SchDoc第2 页 共38 页1.1 PSU.SchDocPWRNET1 NT7 2iT P0PWRNET i GNDAGND GND3V3PWRNETiT P13V3T P2PWRNET iGNDGND3V3C23_CM10uF10VC24_CM10uF10VU_PSU_MAX1831_1V2_ALTPSU_MAX1831_1V2_ALT1V25V0GNDT P3 PWRNET iShared Bypass Caps5V01V2PWRN

3、ET iT P41V2第3 页 共38 页1.1 PSU_MAX1831.SchDoc5V0 1V2U1_PSMAX1831EEEL1_PS2u2, 15A, 4R2, SMDR2_PS10R1%Vfilt2412ININVCCLX 14LX 16LX 3LX 1 FB 8LXFBR1_PS2K7 1%C4_PS2.2uF10VC2_PS470pF50VCOMP56SHDNCOMPPGND 13PGND 15R3_PS27K 1%C5_PS10uF10VC6_PS22uF10VR5_PS100K 1%TOFF7TOFFAGND 9FBSEL 11GNDR4_PS2K7 1%C8_PS10uF10VC1_PS22uF10VC3_PS220uF10VREF 10REF_1V2C7_PS1uF25VGND GND AGND AGND AGND GND GND GND第4 页 共38 页1.2 DB31_Hardware_Kit.SchDocU_MOUNTSDB_MOUNTSPCB 1DB31 BlankPCB Printed Circuit Board (Bare)第5 页 共38 页1.2

4、. DB_MOUNTS.SchDocMH1MOUNTING HOLE 3MMPurPer Logo Top1PurPer MH2MOUNTING HOLE 3MMPurPer Logo Bot1MH3MOUNTING HOLE 3MMPurPer第6 页 共38 页1.3 DB_ByPass.SchDoc3V3C1_MB220uF10VC2_MB220uF10VGNDThese decoupling capacitors are intended to assist the voltage rails on the PCB - where the decoupling capacitors for the FPGA are not close.第7 页 共38 页1.4 DB_Common.SchDocTop Level Schematic For Daughter Boar d Design Bot h FPGA-Only and FPGA + MCUThis De vice Sheet is the same for all designs.It relies on being i

5、nstantiated in a project that contains a device-specific sheet named DEVICES.SchDoc .U_Memory_CommonBus_DaughterBoardNB2_CommonMemoryU_DEVICESDEVICES.SchDocU_MotherBoardConnectorsDB_MotherBoardConnectorsMEM BUSDAU_RESET_SW SLEEP_N SWDAU_RESET_SWSLEEP_NSWBUZZER BUZZERCAN CANU_CommonMemory_TerminationNB2_CommonMemory_TerminationDIPUSER_LEDDIPUSER_LEDMEMUSERIO USERIOJTAG JTAGI2C I2CU_SRAM_K6R4016V1D-TC10T_256Kx16SRAM_256Kx16_TSOP44KEYBOARDMOUSEKEYBOARDMOUSESRAM SRAM1 RS232 RS232SPI SPIU_SRAM_K6R401

6、6V1D-TC10T_256Kx16SRAM_256Kx16_TSOP44CLOCKSPROGRAMCLOCKSPROGRAMSRAM SRAM2 TFT TFTEXT_A EXT_B EXT_CEXT_AEXT_BEXT_CU_DaughterBoard_LEDSDB_LEDSSTATUS_LEDSTATUS_LEDSTATUS_LEDONE_WIRE_DB_PB ONE_WIRE_DBID ONE_WIRE_PIO1ONE_WIRE_DB_PBONE_WIRE_DBIDONE_WIRE_PIO1第8 页 共38 页1.4.1 DEVICES.SchDocU_ FPGAFPGA.SCHDOCBUSSRAM1SRAM2MEM_COMMON DAU_RESET_SWSRAM1 SWSRAM2 BUZZER CANDAU_RESET_SWSWBUZZERCANDIPUSER_LEDDIPUSER_LEDUSERIO USERIOI2C I2CSTATUS_LED STATUS_LEDKEYBOARD MOUSEKEYBOARDMOUSERS232 TFTRS232TFTEXT_A EXT_

7、B EXT_CEXT_AEXT_BEXT_CSPI SPIONE_WIRE_DB_PB ONE_WIRE_DBID ONE_WIRE_PIO1ONE_WIRE_DB_PB CLOCKSONE_WIRE_DBID PROGRAMONE_WIRE_PIO1 JTAGCLOCKSPROGRAMJTAGSLEEP_NDevice Specific Section of Daughter Board DesignThis schematic sheet (plus any child sheets) will contain the device specific parts ofany daughter board designs.This will include any FPGA or MCU devices as well as dedicated power supplies, connectors etc.第9 页 共38 页1.4.1.1 FPGA.SchDocDAUGHTERBOARD I/OJTAGJTAGHARDSOFT TDI TCK TMSTDO TDI TCK TMST

8、DOFPGA_TDIFPGA_TCKFPGA_TMSFPGA_TDONEXUS_TDINEXUS_TCKNEXUS_TMSNEXUS_TDOHOSTPERIPHERALSDAU_RESET_SWDAU_RESET_SWBUZZER BUZZERRS232TXD RTSRXD CTSRS232_TXRS232_RTSRS232_RXRS232_CTSUSER_LED L7.0SW D4.0DIP D7.0LED7.0SW4.0DIP7.0IO35.0USERIO IO35.0EXT_A D49.0EXT_B D49.0EXTEND_A49.0EXTEND_B49.0EXT_C EXTEND_C49.0D49.0DAUGHTERBOARD MEMORYRESOURCES SRAM2_A18.0A18.0 A18.0 SRAM2_D15.0D15.0 D15.0 SRAM2_NOENOE NOE SRAM2_NWESRAM2 NWE SRAM1 NWE SRAM2_NCSNCS NCS SRAM2_NBHENBHE NBHE SRAM2_NBLENBLE NBLESRAM1_A18.0SRAM1_D15.0SRAM1_NOESRAM1_NWESRAM1_

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