vhdl源代码-计数器
十五计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0);END fiveteencout;ARCHITECTURE counter OF fiveteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int '0');ELSIF enable = '1' THENIF(count_int="1110") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="1101") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="1100") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="1011") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="1010") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="1001") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="1000") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="111") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="101") THENcount_int '0');ELSIF enable = '1' THENIF(count_int="11") THENcount_int<="00"ELSEcount_int <= count_int 1;-ELSE- NULL ;-IF (count_int="1001") THEN-count_int<="0000"END IF;END IF;END PROCESS;count <= count_int;- IF (reset='0') then-q<="0000"-ELSIF(clk'event and clk='1') THEN-q<=q 1;-IF (q<="1001") then-q<="0000"-END IF;-IF (reset<='1')THEN-q<="00"-ELSIF-wait until (clk'event and clk='1');-WAIT UNTIL (clk'EVENT AND clk = '1');-WAIT UNTIL (clock'EVENT AND clock = '1');- q<=q '1'-end if;-count<=q;- WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-clock'event and clock='1'-count <= 0;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT riseedge clock = '1'-if (clock'event and clock='1') then-WAIT UNTIL rising_edge(clock);-count <= 1;-WAIT UNTIL (clock'EVENT AND clock = '1');-WAIT UNTIL clock = '1'-if (clock'event and clock='1')then-WAIT UNTIL rising_edge(clock);-count <= 2;-end if;-end if;-end if;- END PROCESS;END counter;