IF语句概述
IFIFIFIF语句概述语句概述语句概述语句概述EDA EDA 技术实用教程技术实用教程 IF语句概述语句概述(1)IF 条件句条件句 Then 顺序语句顺序语句 END IF;(2)IF 条件句条件句 Then 顺序语句顺序语句 ELSE 顺序语句顺序语句 END IF;(3)IF 条件句条件句 Then IF 条件句条件句 Then .END IF END IF(4)IF 条件句条件句 Then 顺序语句顺序语句ELSIF 条件句条件句 Then顺序语句顺序语句.ELSE 顺序语句顺序语句END IF IF语句概述语句概述【例【例6-14】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY control_stmts ISPORT(a,b,c:IN BOOLEAN;output:OUT BOOLEAN);END control_stmts;ARCHITECTURE example OF control_stmts IS BEGIN PROCESS(a,b,c)VARIABLE n:BOOLEAN;BEGIN IF a THEN n:=b;ELSE n:=c;END IF;output=n;END PROCESS;END example;IF语句概述语句概述 输输 入入输输 出出din0 din1 din2 din3 din4 din5 din6 din7 output0 output1 output2 x x x x x x x 0 0 0 0 x x x x x x 0 1 1 0 0 x x x x x 0 1 1 0 1 0 x x x x 0 1 1 1 1 1 0 x x x 0 1 1 1 1 0 0 1 x x 0 1 1 1 1 1 1 0 1 x 0 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1表表6-2 8线线-3线优先编码器真值表线优先编码器真值表 注：注：表中的表中的“x”为任意，类似为任意，类似VHDL中的中的“”值。值。【例【例6-15】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY coder IS PORT(din:IN STD_LOGIC_VECTOR(0 TO 7);output:OUT STD_LOGIC_VECTOR(0 TO 2);END coder;ARCHITECTURE behav OF coder IS SIGNAL SINT:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN PROCESS(din)BEGIN IF(din(7)=0)THEN output=000;ELSIF(din(6)=0)THEN output=100;ELSIF(din(5)=0)THEN output=010;ELSIF(din(4)=0)THEN output=110;ELSIF(din(3)=0)THEN output=001;ELSIF(din(2)=0)THEN output=101;ELSIF(din(1)=0)THEN output=011;ELSE output=111;END IF；END PROCESS；END behav;谢谢观看！谢谢观看！谢谢观看！谢谢观看！EDA EDA 技术实用教程技术实用教程
