Designing digital downconverters

38 www.rfdesign.com May 2006Design Tools/SoftwareDesigning digital downconverters A key problem with traditional RF design methods is that errors are frequently not detected until modules can be physically tested at the prototype stage. Model-based design can address this problem by providing an environment for creating executable specications that provide a high-level view of the design.1 This article will demonstrate how model-based design was used to design a digital downconverter for a software-dened radio (SDR).By Brian Ogilvie and Paul PachecoA survey by Collet International Research showed that only 39% of designs were bug-free at rst silicon while 60% contained logic or functional aws2. Detecting aws this late in the design cycle is expensive since, according to Maxeld and Goyal, “each delay in detection and correction of a design problem makes it an order of magnitude more expensive to x.”3Using model-based design, algorithm developers, RF designers, software and hardware engineers and other development team members can cooperate to make trade offs and evaluate solutions with the goal of enhancing performance and reducing costs. Components of digital radioIn a simplied digital radio design, the high-frequency signal received from the antenna rst passes through an RF section fol-lowed by analog-to-digital conversion. In the case of a global system for mobile communications (GSM) system, the frequency of the incoming signal at this stage is around 70 MHz. This high-frequency signal then passes through a digital downconverter (DDC), which performs frequency translation and produces the corresponding baseband signal. In the case of a GSM system, the baseband frequency is around 270 kHz. The digital radio then recreates the audio signal after demodulating the baseband signal.GSM DDC design specicationsThe digital downconverter (DDC) is a key component of a digital radio. The DDC performs the frequency translation neces-sary to convert the high sample rates down to lower sample rates for further and easier processing. The frequency and performance specications of the DDC vary based on the actual application, but are invariably stringent and hard to design and implement. In this GSM example, we consider the specications of the GrayChip GC4016 Quad DDC chip.4The DDC in this implementation operates at approximately 70 MHz and must decimate the rate down to 270 kHz. Figure 4 shows a graphical representation of the out-of-band rejection mask specications of a DDC to be used in GSM systems.Figure 1. Typical DDC out-of-band rejection mask for GSM applications.Adjacent Band RejectionBlocker RequirementsFrequency (MHz)Magnitude(dB)0-20-40-60-80-100-1200 0.2 0.4 0.6 0.8 1NCOCIC DecimatorCompensatingFIRProgrammableFIRFINEGainRateConversionOut 1GSMSourceA/DxFigure 2. Schematic representation of a DDC for GSM applications.Frequency (MHz)Magnitude(dB)0-50-100-150-200-250-300-350-4000 5 10 15 20 25 30Figure 3. CIC lter response (normalized).40 www.rfdesign.com May 2006The GSM passband bandwidth of interest is 80 kHz. The GSM requirements for the overall response of the three-stage multirate lter of the DDC includes: decimating the input signal by 256; less than 0.1 dB of peak-to-peak passband ripple; and 18 dB of attenuation at 100 kHz. Digital downconverter (DDC)One possible schematic representation of a GSM DDC is shown in Figure 3 and consists of a numeric controlled oscillator (NCO) and a mixer to quadrature downconvert the input signal to base-band. The baseband signal is then low-pass ltered by a cascaded integrator-comb (CIC) filter followed by two finite impulse response (FIR) decimating lters to achieve a low sample rate of 270 kHz ready for demodulation. The nal stage often includes a re-sampler, which interpolates or decimates the signal to achieve the desired sample rate depending on the application. Further ltering can also be achieved with the re-sampler. This design concentrates on the three-stage multirate decimation lter, which includes a CIC and two decimating FIR lters. The CIC lter is suitable for this high-speed application (69.333 MHz) because of its ability to achieve high decimation factors and the fact that it's implemented without using multipliers.The CIC in this example will perform decimation by 64. The second lter is a 21-tap CIC-compensation FIR lter (CFIR), which has an inverse-sync passband response, and decimates by two. The third-stage lter is a 63-tap FIR lter (PFIR), which ensures that the overall lter response meets the GSM spectral mask. It also decimates by two to achieve an overall decimation factor of 256.We will now attempt to apply the model-based design methodology to design, simulate, implement and verify the DDC specied earlier.Stage 1: lter designThe CIC lter performs moderate spectral ltering to avoid spectral imaging while decimating by 64. The input data type is set to signed arithmetic